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公开(公告)号：US20200211272A1
公开(公告)日：2020-07-02
申请号：US16235517
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX , CARSON BROWNLEE , GABOR LIKTOR
Abstract: Multi-pass apparatus and method for ray tracing shading. For example, one embodiment of an apparatus comprises: graphics processing circuitry to execute a sequence of visibility testing operations related to texels within a texture domain to generate visibility results; a register or memory to store a texel mask; texel mask update circuitry/logic to update the texel mask based on the visibility results, the texel mask comprising a plurality of bits to indicate visibility of the texels within the texture domain, the texel mask update circuitry/logic to set a first bit to indicate whether any bits in the texel mask indicate a visible texel; a shader dispatcher to initiate conditional dispatch operations only if the first bit is set to indicate that at least one bit in the texel mask indicates a visible texel, wherein to perform the conditional dispatch operations, the shader dispatcher is to dispatch texel shaders for only those texels that the texel mask indicates may be visible; and a plurality of execution units (EUs) to execute the shaders dispatched by the shader dispatcher.
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公开(公告)号：US20220327655A1
公开(公告)日：2022-10-13
申请号：US17724299
申请日：2022-04-19
Applicant: Intel Corporation
Inventor： MICHAEL DOYLE , TRAVIS SCHLUESSLER , GABOR LIKTOR , ATSUO KUWAHARA , JEFFERSON AMSTUTZ
IPC: G06T1/20 , G06F16/901 , G06F9/38 , G06F9/50 , G06T15/00
Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
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公开(公告)号：US20220222886A1
公开(公告)日：2022-07-14
申请号：US17557968
申请日：2021-12-21
Applicant: Intel Corporation
Inventor： CARSTEN BENTHIN , GABOR LIKTOR
Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.
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公开(公告)号：US20200211266A1
公开(公告)日：2020-07-02
申请号：US16236245
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , GABOR LIKTOR , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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5.发明申请公开(公告)号：US20180293782A1
公开(公告)日：2018-10-11
申请号：US15482701
申请日：2017-04-07
Applicant: Intel Corporation
Inventor： CARSTEN BENTHIN , GABOR LIKTOR
Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.
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Patent Agency Ranking
公开(公告)号：US20220108518A1
公开(公告)日：2022-04-07
申请号：US17505387
申请日：2021-10-19
Applicant: Intel Corporation
Inventor： KAI XIAO , MICHAEL APODACA , CARSON BROWNLEE , THOMAS RAOUX , JOSHUA BARCZAK , GABOR LIKTOR
Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
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公开(公告)号：US20200211263A1
公开(公告)日：2020-07-02
申请号：US16235906
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , ALEXEY SUPIKOV , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS , MICHAEL DOYLE
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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8.发明申请公开(公告)号：US20200211253A1
公开(公告)日：2020-07-02
申请号：US16236176
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： GABOR LIKTOR , KARTHIK VAIDYANATHAN , JEFFERSON AMSTUTZ , ATSUO KUWAHARA , MICHAEL DOYLE , TRAVIS SCHLUESSLER
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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公开(公告)号：US20200043218A1
公开(公告)日：2020-02-06
申请号：US16056222
申请日：2018-08-06
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , WON-JONG LEE , GABOR LIKTOR , JOHN G. GIERACH , PAWEL MAJEWSKI , PRASOONKUMAR SURTI , CARSTEN BENTHIN , Sven WOOP , THOMAS RAOUX
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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公开(公告)号：US20210327120A1
公开(公告)日：2021-10-21
申请号：US17308828
申请日：2021-05-05
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , GABOR LIKTOR , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , THOMAS RAOUX
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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