公开(公告)号：US20220058853A1

公开(公告)日：2022-02-24

申请号：US17500631

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20200051309A1

公开(公告)日：2020-02-13

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T17/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20230360307A1

公开(公告)日：2023-11-09

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.