公开(公告)号：US11275663B2

公开(公告)日：2022-03-15

申请号：US16896070

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Nimrod Angel ,  Ameya Ambardekar ,  Sapumal Wijeratne ,  Vikas Vij ,  Tod Schiff ,  Alexander Uan-Zo-Li

IPC: G06F1/3296 ,  G06F11/30 ,  G06F11/07 ,  G06F9/30 ,  G06F9/4401

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

公开(公告)号：US20210382805A1

公开(公告)日：2021-12-09

申请号：US16896070

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Nimrod Angel ,  Ameya Ambardekar ,  Sapumal Wijeratne ,  Vikas Vij ,  Tod Schiff ,  Alexander Uan-Zo-Li

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/3296 ,  G06F9/4401 ,  G06F9/30

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).