公开(公告)号：US20240429131A1

公开(公告)日：2024-12-26

申请号：US18824468

申请日：2024-09-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L25/16

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20230253295A1

公开(公告)日：2023-08-10

申请号：US18132801

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L23/481 ,  H01L25/16 ,  H01L24/09 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/17 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20230361003A1

公开(公告)日：2023-11-09

申请号：US18216040

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/822 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/16 ,  H01L24/09 ,  H01L24/17 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20220157694A1

公开(公告)日：2022-05-19

申请号：US17587647

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.