公开(公告)号：US20220108733A1

公开(公告)日：2022-04-07

申请号：US17553439

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Wayson Lowe ,  Ban Wong

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C7/22 ,  G11C11/419

Abstract: A memory circuit includes a column of memory cells. A column selection circuit is coupled to the column of the memory cells through a bit line. The column selection circuit pulls a voltage of the bit line toward a predefined voltage in response to a write control signal during a write operation to at least one of the memory cells in the column of the memory cells. A write enable circuit generates a write enable signal. A regenerative repeater circuit is coupled to the column of the memory cells through the bit line. The regenerative repeater circuit pulls the voltage of the bit line toward the predefined voltage in response to the write enable signal during the write operation.

公开(公告)号：US20210111721A1

公开(公告)日：2021-04-15

申请号：US17128773

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Ban Wong ,  Wayson Lowe

IPC: H03K19/1776 ,  H03K19/17736

Abstract: An integrated circuit includes a memory array circuit, flip-flop circuits, and a write programmable matrix circuit. A first one of the flip-flop circuits is coupled to store one of a first write address signal or a first data input signal. A second one of the flip-flop circuits is coupled to store one of a second write address signal or a second data input signal. A write programmable matrix circuit is coupled to receive signals stored in the flip-flop circuits. The write programmable matrix circuit is coupled to provide a subset of the signals stored in the flip-flop circuits to inputs of the memory array circuit through option conductors in the write programmable matrix circuit during write operations to the memory array circuit.

公开(公告)号：US20200027828A1

公开(公告)日：2020-01-23

申请号：US16586633

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Wayson Lowe ,  Ban Pak Wong

IPC: H01L23/522 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C8/16 ,  H01L27/11

Abstract: An integrated circuit device includes a memory circuit and a via layer that are used to support different memory demands based on a via configuration of the via layer. A first via configuration of the via layer causes the memory circuit of the integrated circuit device to function as a true dual-port memory circuit in a first via configuration. Moreover, a second via configuration of the via layer causes the memory circuit of the integrated circuit device to function as a simple dual-port memory circuit in a second via configuration.

公开(公告)号：US20220014197A1

公开(公告)日：2022-01-13

申请号：US17483026

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Wayson Lowe ,  David Parkhouse ,  Alexander Andreev ,  Ban Wong

IPC: H03K19/0185 ,  H01L27/118

Abstract: An integrated circuit includes first and second routing crossbars. The second routing crossbar includes first conductors routed in a first direction in a first conductive layer and second conductors routed in a second direction that is perpendicular to the first direction in a second conductive layer. A first subset of the first conductors is coupled to the first routing crossbar. The first subset of the first conductors is coupled to a second subset of the first conductors through a first subset of the second conductors that is coupled to the first and second subsets of the first conductors through first vias. The second subset of the first conductors is coupled to a second subset of the second conductors to through second vias. At least one of the first conductors is decoupled from another one of the first conductors by third vias.