公开(公告)号：US20220115315A1

公开(公告)日：2022-04-14

申请号：US17559645

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Ankireddy Nalamalpu ,  Mahesh K. Kumashikar ,  David Parkhouse

IPC: H01L23/528 ,  H01L21/768

Abstract: A reticle-stitched integrated circuit is provided. The reticle-stitched integrated circuit extends over a first die area and a second die area of an integrated circuit wafer. While individually the first die area and the second die area are within their respective reticle limits, collectively the first die area and the second die area exceed the reticle limit. A first layer of the reticle-stitched integrated circuit may have communication wires that remain exclusively in only one of the first die area and the second die area. A second layer of the reticle-stitched integrated circuit may have communication wires that overlap the first die area and the second die area, thereby allowing communication between the two die areas and enabling the reticle-stitched integrated circuit to exceed the limit of the reticle.

公开(公告)号：US20230410897A1

公开(公告)日：2023-12-21

申请号：US18241217

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： David Parkhouse ,  Andy Lee ,  J M Lewis Higgins ,  Yan Cui ,  Shuxian Chen ,  Shankar Sinha

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.

公开(公告)号：US20220014197A1

公开(公告)日：2022-01-13

申请号：US17483026

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Atul Maheshwari ,  Wayson Lowe ,  David Parkhouse ,  Alexander Andreev ,  Ban Wong

IPC: H03K19/0185 ,  H01L27/118

Abstract: An integrated circuit includes first and second routing crossbars. The second routing crossbar includes first conductors routed in a first direction in a first conductive layer and second conductors routed in a second direction that is perpendicular to the first direction in a second conductive layer. A first subset of the first conductors is coupled to the first routing crossbar. The first subset of the first conductors is coupled to a second subset of the first conductors through a first subset of the second conductors that is coupled to the first and second subsets of the first conductors through first vias. The second subset of the first conductors is coupled to a second subset of the second conductors to through second vias. At least one of the first conductors is decoupled from another one of the first conductors by third vias.