公开(公告)号：US20220373734A1

公开(公告)日：2022-11-24

申请号：US17323881

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Sandeep Gaan ,  Srinivas Pietambaram ,  Wenchao Li ,  Kristof Darmawikarta ,  Ankur Agrawal ,  Ravindranath Mahajan

IPC: G02B6/12 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  G02B6/13

Abstract: IC chip package with silicon photonic features integrated onto an interposer along with electrical routing redistribution layers. An active side of an IC chip may be electrically coupled to a first side of the interposer through first-level interconnects. The interposer may include a core (e.g., of silicon or glass) with electrical through-vias extending through the core. The redistribution layers may be built up on a second side of the interposer from the through-vias and terminating at interfaces suitable for coupling the package to a host component through second-level interconnects. Silicon photonic features (e.g., of the type in a photonic integrated circuit chip) may be fabricated within a silicon layer of the interposer using high temperature processing, for example of 350° C., or more. The photonic features may be fabricated prior to the fabrication of metallized redistribution layers, which may be subsequently built-up within dielectric material(s) using lower temperature processing.