公开(公告)号：US20240345324A1

公开(公告)日：2024-10-17

申请号：US18133353

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Kristof Darmawikarta ,  Soham Agarwal ,  Marcel Said ,  Sandeep Gaan

IPC: G02B6/26

CPC classification number: G02B6/26

Abstract: An integrated circuit package includes a substrate with an integrated circuit device mounting surface, and at least one optical fiber mount in the substrate. The optical fiber mount includes a support having at least one optical fiber mounting channel, and the optical fiber mounting channel is configured to mount at least one clad optical fiber.

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20190259631A1

公开(公告)日：2019-08-22

申请号：US16347207

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Kristof Kuwawi Darmawikarta ,  Sri Ranga Sai Boyapati ,  Sandeep Gaan ,  Srinivas V. Pietambaram

IPC: H01L21/48 ,  H01L23/498

Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.

公开(公告)号：US20220373734A1

公开(公告)日：2022-11-24

申请号：US17323881

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Sandeep Gaan ,  Srinivas Pietambaram ,  Wenchao Li ,  Kristof Darmawikarta ,  Ankur Agrawal ,  Ravindranath Mahajan

IPC: G02B6/12 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  G02B6/13

Abstract: IC chip package with silicon photonic features integrated onto an interposer along with electrical routing redistribution layers. An active side of an IC chip may be electrically coupled to a first side of the interposer through first-level interconnects. The interposer may include a core (e.g., of silicon or glass) with electrical through-vias extending through the core. The redistribution layers may be built up on a second side of the interposer from the through-vias and terminating at interfaces suitable for coupling the package to a host component through second-level interconnects. Silicon photonic features (e.g., of the type in a photonic integrated circuit chip) may be fabricated within a silicon layer of the interposer using high temperature processing, for example of 350° C., or more. The photonic features may be fabricated prior to the fabrication of metallized redistribution layers, which may be subsequently built-up within dielectric material(s) using lower temperature processing.

公开(公告)号：US11443885B2

公开(公告)日：2022-09-13

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Pietambaram ,  Sandeep Gaan ,  Sri Ranga Sai Boyapati ,  Prithwish Chatterjee ,  Sameer Paital ,  Rahul Jain ,  Junnan Zhao

IPC: H01F17/00 ,  H01F17/06 ,  H01F41/04 ,  H01F27/28 ,  H01F27/24

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US11291122B2

公开(公告)日：2022-03-29

申请号：US16637545

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Darko Grujicic ,  Rengarajan Shanmugam ,  Sandeep Gaan ,  Adrian Bayraktaroglu ,  Roy Dittler ,  Ke Liu ,  Suddhasattwa Nad ,  Marcel A. Wall ,  Rahul N. Manepalli ,  Ravindra V. Tanikella

IPC: C23C18/38 ,  H05K3/38 ,  C23C18/16 ,  C23C18/18 ,  H01L21/48 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11 ,  H01L23/14

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20250110289A1

公开(公告)日：2025-04-03

申请号：US18479004

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Gang Duan ,  Sandeep Gaan ,  Donald Hammon ,  Wesley B. Morgan

IPC: G02B6/38

Abstract: A ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. The ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. The ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more optical fibers with one or more waveguides of the other device.

公开(公告)号：US20240111093A1

公开(公告)日：2024-04-04

申请号：US17957094

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Sandeep Gaan

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13

Abstract: Various embodiments disclosed relate to routing optical signals from silicon photonics, such as a photonic integrated circuit. The present disclosure includes a glass recirculatory layer with waveguides at varying heights to allow re-routing of such optical signals from silicon photonics, such as a photonic integrated circuit. Re-routing of optical signals can be accomplished in the glass recirculatory layer with reduced losses due to reduced intersections of waveguides therein.

公开(公告)号：US11037802B2

公开(公告)日：2021-06-15

申请号：US16347207

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Sri Ranga Sai Boyapati ,  Sandeep Gaan ,  Srinivas V. Pietambaram

IPC: H01L23/52 ,  H01L21/48 ,  H01L23/498 ,  H05K3/42 ,  H05K3/38

Abstract: Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.

公开(公告)号：US20190006457A1

公开(公告)日：2019-01-03

申请号：US15638044

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert Alan May ,  Sandeep Gaan

IPC: H01L49/02 ,  H01L23/522

Abstract: A semiconductor device may include a plurality of layers of a substrate. A die may be coupled to at least one of the plurality of layers of the substrate. A passive electrical component may be integrally formed within the layers of the substrate. The passive electrical component may be a resistor or a capacitor. One or more conductors may be configured to allow electrical communication between the passive electrical component and the die. The one or more conductors may be integrally formed within the plurality of layers of the substrate.