MULTI-DECK NON-VOLATILE MEMORY ARCHITECTURE WITH IMPROVED WORDLINE BUS AND BITLINE BUS CONFIGURATION

    公开(公告)号:US20220101909A1

    公开(公告)日:2022-03-31

    申请号:US17032191

    申请日:2020-09-25

    申请人: Intel Corporation

    摘要: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.

    Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration

    公开(公告)号:US12087350B2

    公开(公告)日:2024-09-10

    申请号:US17032191

    申请日:2020-09-25

    申请人: Intel Corporation

    摘要: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.