公开(公告)号：US10915320B2

公开(公告)日：2021-02-09

申请号：US16231305

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Xi Chen ,  Manjunath Shevgoor

IPC: G06F9/302 ,  G06F9/315 ,  G06F9/30 ,  G06F9/54 ,  G06F9/38

Abstract: A processor includes an instruction fetch circuit to retrieve instructions from memory, and a decode unit circuit to decode retrieved instructions. The decode unit circuit identifies a shift instruction, accumulates a shift folded immediate value to track a number of bit positions shifted for a source register, and prevents the shift instruction from allocation to an execution unit of the processor.