公开(公告)号：US20250036751A1

公开(公告)日：2025-01-30

申请号：US18375391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bin XING ,  Mona VIJ ,  Rajesh POORNACHANDRAN ,  Barry HUNTLEY ,  Scott CONSTABLE ,  Yuan XIAO ,  Xiang CHENG

IPC: G06F21/54 ,  G06F9/30 ,  G06F21/55

Abstract: In one embodiment, an apparatus comprises a cache to store a plurality of instructions and data associated with a trusted execution environment; instruction processing circuitry to execute the plurality of instructions and process the data, the plurality of instructions including one or more instructions with memory operands, wherein responsive to an interrupt or an exception, the instruction processing circuitry is to pause processing the plurality of instructions and execute a handler; and decode circuitry to partially decode a next instruction of the plurality of instructions to be processed following execution of the handler to determine if the next instruction indicates a memory access and, if so, to calculate at least one corresponding memory address, wherein the partial decode is performed in accordance with one or more constant time programming restrictions.