公开(公告)号：US20220084606A1

公开(公告)日：2022-03-17

申请号：US17023094

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Xiang YANG ,  Guangyu HUANG ,  Narayanan RAMANAN ,  Pranav KALAVADE ,  Ali KHAKIFIROOZ

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C7/02 ,  G11C16/26

Abstract: A method is described. The method includes programming a column of flash storage cells in a direction along the column in which a parasitic transistor that resides between a cell being programmed and an immediately next cell to be programmed has lower resistivity as compared to a corresponding parasitic transistor that exists if the programming were to be performed in an opposite direction along the column.

公开(公告)号：US20210280261A1

公开(公告)日：2021-09-09

申请号：US16808955

申请日：2020-03-04

Applicant: Intel Corporation

Inventor： Xiang YANG

IPC: G11C16/34 ,  G06F3/06

Abstract: An apparatus is described. The apparatus includes a non volatile memory chip. The non volatile memory chip includes an interface to receive access commands, a three dimensional array of non volatile storage cells, and, a controller to orchestrate removal of charge in a column of stacked ones of the non volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount. The removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column. Cells that are coupled to the column are programmed in the particular direction. Disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction.

公开(公告)号：US20210104285A1

公开(公告)日：2021-04-08

申请号：US16591978

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Xiang YANG ,  Shantanu R. RAJWADE ,  Ali KHAKIFIROOZ ,  Tarek Ahmed AMEEN BESHARI

IPC: G11C16/34 ,  G11C16/08

Abstract: An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.