公开(公告)号：US20250156356A1

公开(公告)日：2025-05-15

申请号：US18834582

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Somnath PAUL ,  Muhammad M. KHELLAH ,  Nilesh JAIN ,  Gopi Krishna JHA ,  Ravishankar IYER ,  Theodore WILLKE ,  Mariano TEPPER ,  Maria Cecilia AGUERREBERE OTEGUI ,  Nagabhushan CHITLUR ,  Suresh THIRUMANDAS ,  Ananthan AYYASAMY ,  Sujoy SEN ,  Xiao HU

IPC: G06F13/40 ,  G06F13/16

Abstract: Examples include techniques to utilize near memory compute circuitry for memory-bound workloads. Examples include the near memory compute circuitry being resident on an input/output (I/O) arranged to couple with a plurality of memory devices configured as a memory pool that is accessible to a host central processing unit (CPU) through the I/O switch. The near memory compute circuitry may receive a request to obtain data from the memory pool and generate a result that is made available to the host CPU to facilitate acceleration of a memory-bound workload.

公开(公告)号：US20180225254A1

公开(公告)日：2018-08-09

申请号：US15506070

申请日：2014-09-25

Applicant: INTEL CORPORATION

Inventor： Xiao HU ,  Xiang ZHOU

IPC: G06F15/167 ,  H04L12/46 ,  G06F12/02 ,  G06F9/455

CPC classification number: G06F15/167 ,  G06F9/45558 ,  G06F12/0223 ,  G06F2009/45595 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/163 ,  H04L12/4641

Abstract: Technologies for network communication using pooled memory include a computing rack having a pooled memory enclosure with a pooled memory controller and a compute enclosure having two or more compute nodes. A first compute node determines a destination virtual network interface controller identifier (vNIC ID) associated with a destination network address. The first compute node transmits a send message to the pooled memory controller that includes the destination vNIC ID and a sender physical address of packet data within the pooled memory. The pooled memory controller transmits a receive message to a second compute node associated with the destination vNIC ID. The second compute node transmits a receiver physical address of a receive buffer within the pooled memory to the pooled memory controller. The pooled memory controller copies the packet data from the sender physical address to the receiver physical address. Other embodiments are described and claimed.

公开(公告)号：US20210350234A1

公开(公告)日：2021-11-11

申请号：US17254150

申请日：2019-01-28

Applicant: INTEL CORPORATION

Inventor： Weifeng YAO ,  Xiao HU ,  Hongpeng MA ,  Yanan LIU ,  Huan H. ZHOU ,  Xiaokun YU ,  Zijie LU

IPC: G06N3/08 ,  G06N3/04 ,  G06K9/62

Abstract: Various embodiments are generally directed to techniques to detect fusible operators with machine learning, such as by evaluating a set of operators in a graph of a machine learning model to identify fusion candidates comprising subgraphs of the graph with two or more operators to combine, for instance. Some embodiments are particularly directed to utilizing a machine learning classifier to evaluate fusion candidates using a set of features of the fusion candidate.