公开(公告)号：US20240168717A1

公开(公告)日：2024-05-23

申请号：US18083366

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Yong JIANG ,  Chengxi WU ,  Ruiqi YANG ,  Xiaodong QIU ,  Xiaoxi CHEN ,  Zilan LIANG ,  Xiaoxuan YANG

IPC: G06F7/544 ,  G06F7/499

CPC classification number: G06F7/5443 ,  G06F7/49942

Abstract: A processor of an aspect is to perform operations corresponding to an unsigned integer multiply-accumulate instruction. The unsigned integer multiply-accumulate instruction is to indicate a first unsigned integer, a second unsigned integer, a first register that is have a third unsigned integer, and a second register. The operations include to multiply the first unsigned integer and the second unsigned integer to generate a product and add the product and the third unsigned integer to generate a sum. The operations also include to store a first portion of the sum in the second register. The first portion of the sum includes M least significant bits of the sum. The operations also include to store a second portion of the sum in the first register. The second portion of the sum includes all bits of the sum that are more significant than the M least significant bits. Other processors are also disclosed.

公开(公告)号：US20220091934A1

公开(公告)日：2022-03-24

申请号：US17544085

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Lei CHEN ,  Liyang LING ,  Xiaodong QIU ,  Yong JIANG

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.