公开(公告)号：US20240168717A1

公开(公告)日：2024-05-23

申请号：US18083366

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Yong JIANG ,  Chengxi WU ,  Ruiqi YANG ,  Xiaodong QIU ,  Xiaoxi CHEN ,  Zilan LIANG ,  Xiaoxuan YANG

IPC: G06F7/544 ,  G06F7/499

CPC classification number: G06F7/5443 ,  G06F7/49942

Abstract: A processor of an aspect is to perform operations corresponding to an unsigned integer multiply-accumulate instruction. The unsigned integer multiply-accumulate instruction is to indicate a first unsigned integer, a second unsigned integer, a first register that is have a third unsigned integer, and a second register. The operations include to multiply the first unsigned integer and the second unsigned integer to generate a product and add the product and the third unsigned integer to generate a sum. The operations also include to store a first portion of the sum in the second register. The first portion of the sum includes M least significant bits of the sum. The operations also include to store a second portion of the sum in the first register. The second portion of the sum includes all bits of the sum that are more significant than the M least significant bits. Other processors are also disclosed.