公开(公告)号：US20180307438A1

公开(公告)日：2018-10-25

申请号：US15719922

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Randy Huang ,  Yeong Tat Liew ,  Jason Gee Hock Ong

IPC: G06F3/06 ,  G06F17/16 ,  G06F7/523 ,  G06F5/08 ,  G06F5/06 ,  G06F5/14 ,  G06F15/80

Abstract: A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

公开(公告)号：US10853034B2

公开(公告)日：2020-12-01

申请号：US16147084

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Jason Gee Hock Ong ,  Yeong Tat Liew ,  Carl Ebeling ,  Vamsi Nalluri

IPC: G06F7/523

Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as an instance specific version or a non-instance specific version. The instance specific version might also be fully enumerated so that the hardware doesn't have to be redesigned assuming all possible unique multiplier values are implemented. Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. CFMM circuitry configured in this way can be used to support convolution neural networks or any operation that requires a straight common factor multiply. Any adder component with the CFMM circuitry may be implemented using bit-serial adders. The bit-serial adders may be further connected in a tree in CNN applications to sum together many input streams.

公开(公告)号：US10585621B2

公开(公告)日：2020-03-10

申请号：US15719922

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Randy Huang ,  Yeong Tat Liew ,  Jason Gee Hock Ong

IPC: G06F17/30 ,  G06F3/06 ,  G06F17/16 ,  G06F7/523 ,  G06F5/08 ,  G06F5/06 ,  G06F15/80 ,  G06F5/14 ,  G06F15/76 ,  G06N3/063

Abstract: A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

公开(公告)号：US20190303103A1

公开(公告)日：2019-10-03

申请号：US16147084

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Jason Gee Hock Ong ,  Yeong Tat Liew ,  Carl Ebeling ,  Vamsi Nalluri

IPC: G06F7/523

Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as an instance specific version or a non-instance specific version. The instance specific version might also be fully enumerated so that the hardware doesn't have to be redesigned assuming all possible unique multiplier values are implemented. Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. CFMM circuitry configured in this way can be used to support convolution neural networks or any operation that requires a straight common factor multiply. Any adder component with the CFMM circuitry may be implemented using bit-serial adders. The bit-serial adders may be further connected in a tree in CNN applications to sum together many input streams.