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公开(公告)号：US10074409B2
公开(公告)日：2018-09-11
申请号：US15421090
申请日：2017-01-31
Applicant: Intel Corporation
Inventor： Simon Finn , Carl Ebeling
CPC classification number: G11C7/1012 , G06F5/06 , G11C7/1006 , G11C7/1045 , G11C7/20 , G11C8/00 , G11C19/28
Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.
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公开(公告)号：US10853034B2
公开(公告)日：2020-12-01
申请号：US16147084
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Thiam Khean Hah , Jason Gee Hock Ong , Yeong Tat Liew , Carl Ebeling , Vamsi Nalluri
IPC: G06F7/523
Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as an instance specific version or a non-instance specific version. The instance specific version might also be fully enumerated so that the hardware doesn't have to be redesigned assuming all possible unique multiplier values are implemented. Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. CFMM circuitry configured in this way can be used to support convolution neural networks or any operation that requires a straight common factor multiply. Any adder component with the CFMM circuitry may be implemented using bit-serial adders. The bit-serial adders may be further connected in a tree in CNN applications to sum together many input streams.
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公开(公告)号：US20190303748A1
公开(公告)日：2019-10-03
申请号：US15942091
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Thiam Khean Hah , Carl Ebeling , Vamsi Nalluri
Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as a instance specific version (where at least some portion of the hardware has to be redesigned if the multipliers change) or a non-instance specific version (where the CFMM circuitry can work with arbitrary multipliers without having to redesign the hardware). Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. The CFMM circuitry may include a multiplier circuit that effectively multiplies the common factor by predetermined fixed constants to generate partial products and may further include shifting and add/subtract circuits for processing and combining the partial products to generate corresponding final output products. CFMM circuitry configured in this way can be used to support convolution neural networks or any operation that requires a straight common factor multiply.
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Patent Agency Ranking
公开(公告)号：US20190303103A1
公开(公告)日：2019-10-03
申请号：US16147084
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Thiam Khean Hah , Jason Gee Hock Ong , Yeong Tat Liew , Carl Ebeling , Vamsi Nalluri
IPC: G06F7/523
Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as an instance specific version or a non-instance specific version. The instance specific version might also be fully enumerated so that the hardware doesn't have to be redesigned assuming all possible unique multiplier values are implemented. Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. CFMM circuitry configured in this way can be used to support convolution neural networks or any operation that requires a straight common factor multiply. Any adder component with the CFMM circuitry may be implemented using bit-serial adders. The bit-serial adders may be further connected in a tree in CNN applications to sum together many input streams.
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公开(公告)号：US11256979B2
公开(公告)日：2022-02-22
申请号：US15942091
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Thiam Khean Hah , Carl Ebeling , Vamsi Nalluri
Abstract: An integrated circuit that includes common factor mass multiplier (CFMM) circuitry is provided that multiplies a common factor operand by a large number of multiplier operands. The CFMM circuitry may be implemented as a instance specific version (where at least some portion of the hardware has to be redesigned if the multipliers change) or a non-instance specific version (where the CFMM circuitry can work with arbitrary multipliers without having to redesign the hardware). Either version can be formed on a programmable integrated circuit or an application-specific integrated circuit. The CFMM circuitry may include a multiplier circuit that effectively multiplies the common factor by predetermined fixed constants to generate partial products and may further include shifting and add/subtract circuits for processing and combining the partial products to generate corresponding final output products. CFMM circuitry configured in this way can be used to support convolution neural networks or any operation that requires a straight common factor multiply.
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公开(公告)号：US10423747B2
公开(公告)日：2019-09-24
申请号：US15422834
申请日：2017-02-02
Applicant: Intel Corporation
Inventor： Scott J. Weber , Carl Ebeling
IPC: G06F17/50
Abstract: A method for designing a system on a target device includes modifying a circuit to enable the circuit to support a plurality of threads at an instant of time. An interface is generated that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein at least one of the modifying and the generating is performed by a processor.
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公开(公告)号：US20180218760A1
公开(公告)日：2018-08-02
申请号：US15421090
申请日：2017-01-31
Applicant: Intel Corporation
Inventor： Simon Finn , Carl Ebeling
CPC classification number: G06F5/06 , G11C7/1006 , G11C7/1045 , G11C7/20 , G11C19/28
Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.
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公开(公告)号：US20180218103A1
公开(公告)日：2018-08-02
申请号：US15422834
申请日：2017-02-02
Applicant: Intel Corporation
Inventor： Scott J. Weber , Carl Ebeling
IPC: G06F17/50
Abstract: A method for designing a system on a target device includes modifying a circuit to enable the circuit to support a plurality of threads at an instant of time. An interface is generated that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein at least one of the modifying and the generating is performed by a processor.
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