公开(公告)号：US11698929B2

公开(公告)日：2023-07-11

申请号：US16207065

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Tsung-Yuan C. Tai ,  Yipeng Wang ,  Raghu Kondapalli ,  Alexander Bachmutsky ,  Yifan Yuan

IPC: G06F7/00 ,  G06F16/901 ,  G06F16/903 ,  G06F16/906

CPC classification number: G06F16/9017 ,  G06F16/906 ,  G06F16/90335

Abstract: A central processing unit can offload table lookup or tree traversal to an offload engine. The offload engine can provide hardware accelerated operations such as instruction queueing, bit masking, hashing functions, data comparisons, a results queue, and a progress tracking. The offload engine can be associated with a last level cache. In the case of a hash table lookup, the offload engine can apply a hashing function to a key to generate a signature, apply a comparator to compare signatures against the generated signature, retrieve a key associated with the signature, and apply the comparator to compare the key against the retrieved key. Accordingly, a data pointer associated with the key can be provided in the result queue. Acceleration of operations in tree traversal and tuple search can also occur.

公开(公告)号：US11709774B2

公开(公告)日：2023-07-25

申请号：US16986094

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yifan Yuan ,  Yipeng Wang ,  Tsung-Yuan C. Tai ,  Tony Hurson

IPC: G06F13/16 ,  G06F12/0804 ,  G06F16/23 ,  G06F12/08

CPC classification number: G06F12/0804 ,  G06F13/1668 ,  G06F16/2365

Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory. In some examples, the cache comprises one or more of: a level-0 (L0), level-1 (L1), level-2 (L2), or last level cache (LLC) and the non-volatile memory comprises one or more of: volatile memory that is part of an Asynchronous DRAM Refresh (ADR) domain, persistent memory, battery-backed memory, or memory device whose state is determinate even if power is interrupted to the memory device. In some examples, based on receipt of a second received packet that includes a request to persist data, the packet processing circuitry is to request that data stored in a memory buffer be copied to the non-volatile memory.