公开(公告)号：US11483184B2

公开(公告)日：2022-10-25

申请号：US17119684

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Yikui Dong ,  Shenggao Li

IPC: H04L25/03

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

公开(公告)号：US20230198546A1

公开(公告)日：2023-06-22

申请号：US17556742

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Yikui Dong

IPC: H03M7/16

CPC classification number: H03M7/165 ,  H03K19/20

Abstract: Some embodiments include an encoder to convert a thermometer code into a binary code output information or a Gray code output information. The encoder supports blind input swapping, such that it provides correct output information without prior knowledge of the input swapping. Some embodiments also include a truth table that has additional rows to describe output information when input information at inputs of the encoder is swapped. The encoder includes symmetrical logic functions with respect to information at its inputs as building blocks.

公开(公告)号：US12028191B2

公开(公告)日：2024-07-02

申请号：US17951562

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Yikui Dong ,  Shenggao Li

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03019

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

公开(公告)号：US20230019127A1

公开(公告)日：2023-01-19

申请号：US17951562

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Yikui Dong ,  Shenggao Li

IPC: H04L25/03

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.

公开(公告)号：US20220191069A1

公开(公告)日：2022-06-16

申请号：US17119684

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Yikui Dong ,  Shenggao Li

IPC: H04L25/03

Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.