中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.019 seconds)

    Programmable clock data recovery (CDR) system including multiple phase error control paths
    1.
    发明授权
    Programmable clock data recovery (CDR) system including multiple phase error control paths 有权

    公开(公告)号：US10523411B2

    公开(公告)日：2019-12-31

    申请号：US15939795

    申请日：2018-03-29

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Ji Chen ,  Michael De Vita ,  Fulvio Spagna ,  Guluke Tong

    IPC: H04L7/033 ,  G06F13/40 ,  G06F13/42 ,  H03L7/089 ,  H03L7/091

    Abstract: Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.

    Phase frequency detector
    2.
    发明授权
    Phase frequency detector 有权

    公开(公告)号：US10374616B2

    公开(公告)日：2019-08-06

    申请号：US15991584

    申请日：2018-05-29

    Applicant: Intel Corporation

    Inventor： Wenyan Vivian Jia ,  Shenggao Li ,  Fulvio Spagna

    IPC: H03L7/087 ,  H03D13/00 ,  G04F10/00

    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

    Supply voltage adaptation via decision feedback equalizer
    4.
    发明授权
    Supply voltage adaptation via decision feedback equalizer 有权

    公开(公告)号：US10075308B2

    公开(公告)日：2018-09-11

    申请号：US15282603

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Ji Chen

    IPC: H04L27/10 ,  H04L25/03 ,  H04L29/06

    CPC classification number: H04L25/03057 ,  H04L25/03019 ,  H04L25/03885 ,  H04L69/28

    Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuity coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

    CIRCUITS FOR DIGITAL AND ANALOG CONTROLLED OSCILLATORS
    5.
    发明申请
    CIRCUITS FOR DIGITAL AND ANALOG CONTROLLED OSCILLATORS 有权
    数字和模拟控制振荡器的电路

    公开(公告)号：US20160191026A1

    公开(公告)日：2016-06-30

    申请号：US14583679

    申请日：2014-12-27

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Sujatha Gowder

    IPC: H03K3/03 ,  H03L7/099

    CPC classification number: H03K3/0315 ,  H03B5/00 ,  H03B5/124 ,  H03B5/1246 ,  H03B5/1278 ,  H03K5/00 ,  H03L7/07 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/18

    Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.

    Abstract translation: 电路可以包括第一节点，环形振荡器，调节器和Kvcc补偿电路。 第一节点可以是为电路提供电源电压的供电节点。 环形振荡器可以由逆变器形成。 调节器可以在第一节点和第二节点之间使用单个晶体管来为振荡器供电。 K补偿电路可以用于向振荡器提供取决于第一电源节点处的电源的可变容性负载，并且当第一节点电源上升时，可以将振荡器频率降低。

    OPEN-LOOP VOLTAGE REGULATION AND DRIFT COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR (DCO)
    6.
    发明申请
    OPEN-LOOP VOLTAGE REGULATION AND DRIFT COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR (DCO) 有权
    数字控制振荡器（DCO）的开环电压调节和缓冲补偿

    公开(公告)号：US20160094231A1

    公开(公告)日：2016-03-31

    申请号：US14498728

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Guluke Tong ,  Sujatha B. Gowder ,  Fulvio Spagna

    IPC: H03L7/099 ,  H03L7/093 ,  H03L7/24

    CPC classification number: H03L7/0991 ,  H03L1/00 ,  H03L1/022 ,  H03L5/00 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/24 ,  H03L2207/06

    Abstract: Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). in embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

    Abstract translation: 实施例包括用于数字控制振荡器（DCO）的开环电压调节和漂移补偿的装置，方法和系统。 在实施例中，通信电路可以包括DCO，开环电压调节器和校准电路。 开环稳压器可以接收校准电压并且可以产生调节电压。 调节电压可以传递到DCO。 在校准模式期间，校准电路可以将调节电压与参考电压进行比较，并根据比较调节校准电压，以将调节电压提供给目标值。 在监视模式期间，校准电路可以接收用于调谐DCO的调谐码，并且基于调谐码的值进一步调整校准电压。

    Circuits for digital and analog controlled oscillators
    7.
    发明授权
    Circuits for digital and analog controlled oscillators 有权

    公开(公告)号：US10727818B2

    公开(公告)日：2020-07-28

    申请号：US15979240

    申请日：2018-05-14

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Sujatha Gowder

    IPC: H03K3/03 ,  H03B5/00 ,  H03L7/099 ,  H03B5/12 ,  H03L7/18 ,  H03L7/093 ,  H03K5/00 ,  H03L7/07

    Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.

    CIRCUITS FOR DIGITAL AND ANALOG CONTROLLED OSCILLATORS
    10.
    发明申请
    CIRCUITS FOR DIGITAL AND ANALOG CONTROLLED OSCILLATORS 审中-公开

    公开(公告)号：US20180269859A1

    公开(公告)日：2018-09-20

    申请号：US15979240

    申请日：2018-05-14

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Sujatha Gowder

    IPC: H03K3/03 ,  H03B5/00 ,  H03B5/12 ,  H03L7/18 ,  H03K5/00 ,  H03L7/07 ,  H03L7/093 ,  H03L7/099

    Abstract: A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.

Patent Agency Ranking