公开(公告)号：US20190305102A1

公开(公告)日：2019-10-03

申请号：US15943567

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Ying PANG

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28

Abstract: A PMOS gate structure is described. The PMOS gate structure includes a trench, a high-k metal layer on a bottom and on sidewalls of the trench and a flourine free tungsten layer on the surface of the high-k metal. The PMOS gate structure also includes a metal layer in a space in the n-type work function metal.

公开(公告)号：US20200219775A1

公开(公告)日：2020-07-09

申请号：US16631352

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Ying PANG ,  Florian GSTREIN ,  Dan S. LAVRIC ,  Ashish AGRAWAL ,  Robert NIFFENEGGER ,  Padmanava SADHUKHAN ,  Robert W. HEUSSNER ,  Joel M. GREGIE

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.