公开(公告)号：US11949595B2

公开(公告)日：2024-04-02

申请号：US16913433

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Yonatan Meir Levitt ,  Gaspar Mora Porta

IPC: H04L12/743 ,  H04L12/46 ,  H04L12/747 ,  H04L45/00 ,  H04L45/74 ,  H04L45/7453

CPC classification number: H04L45/7453 ,  H04L12/4675 ,  H04L45/34 ,  H04L45/742

Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.

公开(公告)号：US20200336424A1

公开(公告)日：2020-10-22

申请号：US16913433

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Yonatan Meir Levitt ,  Gaspar Mora Porta

IPC: H04L12/743 ,  H04L12/747 ,  H04L12/46 ,  H04L12/721

Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.