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    Apparatus and methods for implementing cluster-wide operational metrics access for coordinated agile scheduling
    1.
    发明授权
    Apparatus and methods for implementing cluster-wide operational metrics access for coordinated agile scheduling 有权

    公开(公告)号：US10547527B2

    公开(公告)日：2020-01-28

    申请号：US15283314

    申请日：2016-10-01

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Raj K. Ramanujan ,  Gaspar Mora Porta ,  Daniel Rivas Barragan

    IPC: H04L12/26 ,  H04L29/08 ,  H04L12/911

    Abstract: Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber nodes or network components in a managed cluster and to subscribe, via a metrics subscription request, to receive from one or more publisher nodes or network components in the managed cluster, metrics associated with the one or more publisher nodes or network components. The metrics to be stored in a dedicated location of the memory. The provision and subscription of metrics may be made using new protocols added to Layer 4 or transport layer of a network communication model and/or over a dedicated communication channel. The dedicated communication channel may be of low bandwidth with fixed priority and deterministic latency.

    Tier-Aware Read and Write
    3.
    发明申请
    Tier-Aware Read and Write 审中-公开

    公开(公告)号：US20190004701A1

    公开(公告)日：2019-01-03

    申请号：US15640943

    申请日：2017-07-03

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Nicolae O. Popovici ,  Charles A. Giefer ,  Gaspar Mora Porta ,  Thomas Willhalm

    IPC: G06F3/06 ,  H04L29/06

    Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.

    Managing starvation and congestion in a two-dimensional network having flow control
    4.
    发明授权
    Managing starvation and congestion in a two-dimensional network having flow control 有权
    在具有流量控制的二维网络中管理饥饿和拥塞

    公开(公告)号：US08867559B2

    公开(公告)日：2014-10-21

    申请号：US13629351

    申请日：2012-09-27

    Applicant: Intel Corporation

    Inventor： Donglai Dai ,  Andres Mejia ,  Gaspar Mora Porta

    IPC: H04L12/28

    CPC classification number: H04L47/6275 ,  H04L47/6215

    Abstract: An apparatus that includes input ports, input buffers coupled with respective input ports, output ports, and routing control circuitry coupled with the input ports, the input buffers and/or the output ports. The plurality of input buffers and the plurality of output ports, the routing control circuitry to maintain a two-tier priority scheme having at least two queues for prioritizing requests stored in the plurality of input buffers.

    Abstract translation: 一种装置，包括输入端口，与相应输入端口耦合的输入缓冲器，输出端口以及与输入端口，输入缓冲器和/或输出端口耦合的路由控制电路。 多个输入缓冲器和多个输出端口，路由控制电路用于维护具有至少两个队列的两层优先级方案，用于对存储在多个输入缓冲器中的请求进行优先级排序。

    Reflection routing as a framework for adaptive modular load balancing for multi-hierarchy network on chips
    7.
    发明授权
    Reflection routing as a framework for adaptive modular load balancing for multi-hierarchy network on chips 有权

    公开(公告)号：US11949595B2

    公开(公告)日：2024-04-02

    申请号：US16913433

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Yonatan Meir Levitt ,  Gaspar Mora Porta

    IPC: H04L12/743 ,  H04L12/46 ,  H04L12/747 ,  H04L45/00 ,  H04L45/74 ,  H04L45/7453

    CPC classification number: H04L45/7453 ,  H04L12/4675 ,  H04L45/34 ,  H04L45/742

    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.

    Mechanism to control resource utilization with adaptive routing
    8.
    发明授权
    Mechanism to control resource utilization with adaptive routing 有权
    利用自适应路由控制资源利用的机制

    公开(公告)号：US09294403B2

    公开(公告)日：2016-03-22

    申请号：US14125707

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Andres Mejia ,  Donglai Dai ,  Gaspar Mora Porta

    IPC: H04L12/801 ,  H04L12/935 ,  H04L12/707 ,  H04L12/729 ,  H04L12/751

    CPC classification number: H04L47/12 ,  H04L45/10 ,  H04L45/125 ,  H04L45/18 ,  H04L45/22 ,  H04L47/11 ,  H04L49/251 ,  H04L49/30 ,  H04L49/3018

    Abstract: Methods and apparatus relating to techniques for controlling resource utilization with adaptive routing are described. In one embodiment, an output port for transmission of an incoming message that is to be received at an input port is determined at routing logic. The routing logic selects the output port from a first output port and a second output port based on congestion information that is detected at one or more other routing logic communicatively coupled to the routing logic. The first output port provides a deterministic route for the incoming message and the second output port provides an adaptive route for the incoming message. Other embodiments are also disclosed.

    Abstract translation: 描述了与利用自适应路由控制资源利用的技术有关的方法和装置。 在一个实施例中，用于传输要在输入端口接收的输入消息的输出端口在路由逻辑处被确定。 基于通信地耦合到路由逻辑的一个或多个其他路由逻辑检测到的拥塞信息，路由逻辑从第一输出端口和第二输出端口选择输出端口。 第一个输出端口为传入消息提供确定性路由，第二个输出端口为传入消息提供一个自适应路由。 还公开了其他实施例。

    REFLECTION ROUTING AS A FRAMEWORK FOR ADAPTIVE MODULAR LOAD BALANCING FOR MULTI-HIERARCHY NETWORK ON CHIPS
    9.
    发明申请
    REFLECTION ROUTING AS A FRAMEWORK FOR ADAPTIVE MODULAR LOAD BALANCING FOR MULTI-HIERARCHY NETWORK ON CHIPS 审中-公开

    公开(公告)号：US20200336424A1

    公开(公告)日：2020-10-22

    申请号：US16913433

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Yonatan Meir Levitt ,  Gaspar Mora Porta

    IPC: H04L12/743 ,  H04L12/747 ,  H04L12/46 ,  H04L12/721

    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.

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