公开(公告)号：US10096610B1

公开(公告)日：2018-10-09

申请号：US15721544

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： John Hopkins ,  Younghee Kim ,  Jie Li ,  Yu Yuwen ,  Ramey Abdelrahaman ,  Kunal Shrotri

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L29/10 ,  H01L29/788

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.