公开(公告)号：US10217755B2

公开(公告)日：2019-02-26

申请号：US15477040

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Kunal Shrotri ,  John Hopkins ,  Darwin Franseda Fan

IPC: G11C16/04 ,  H01L27/11524 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L27/12

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

公开(公告)号：US20180286876A1

公开(公告)日：2018-10-04

申请号：US15477040

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Changhan Kim ,  Kunal Shrotri ,  John Hopkins ,  Darwin Franseda Fan

IPC: H01L27/11524 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L27/11524 ,  H01L27/1157 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of insulative layers vertically spaced apart from one another. The memory component can also include a vertically oriented conductive channel extending through the plurality of insulative layers. In addition, the memory component can include a charge storage structure disposed between adjacent insulative layers. The charge storage structure can have a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side. A length of the first side can be greater than a length of the second side. In another example, the vertical cross-section of the charge storage structure comprises a non-rectangular shape, such as a trapezoid shape. Associated systems and methods are also disclosed.

公开(公告)号：US10096610B1

公开(公告)日：2018-10-09

申请号：US15721544

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： John Hopkins ,  Younghee Kim ,  Jie Li ,  Yu Yuwen ,  Ramey Abdelrahaman ,  Kunal Shrotri

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L29/10 ,  H01L29/788

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.