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公开(公告)号:US20240321887A1
公开(公告)日:2024-09-26
申请号:US18187801
申请日:2023-03-22
Applicant: Intel Corporation
Inventor: Tao Chu , Yanbin Luo , Yusung Kim , Minwoo Jang , Paul Packan , Guowei Xu , Chiao-Ti Huang , Robin Chao , Feng Zhang , Yang Zhang , Zheng Guo
IPC: H01L27/092 , H01L29/49
CPC classification number: H01L27/0922 , H01L29/4966
Abstract: An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.