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    INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES 有权

    公开(公告)号：US20250140649A1

    公开(公告)日：2025-05-01

    申请号：US18498340

    申请日：2023-10-31

    Applicant: Intel corporation

    Inventor： Feng Zhang ,  Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Guowei Xu ,  Ting-Hsiang Hung ,  Chiao-Ti Huang ,  Robin Chao ,  Chia-Ching Lin ,  Yang Zhang ,  Kan Zhang

    IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/778 ,  H01L29/786

    Abstract: An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure. The backside semiconductor structure may be over a backside via that can couple the backside semiconductor structure to a backside metal layer.

    LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
    2.
    发明申请
    LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES 有权

    公开(公告)号：US20250087530A1

    公开(公告)日：2025-03-13

    申请号：US18463436

    申请日：2023-09-08

    Applicant: Intel Corporation

    Inventor： Chiao-Ti Huang ,  Tao Chu ,  Guowei Xu ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Ting-Hsiang Hung ,  Anand Murthy

    IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

    Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.

    BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION
    4.
    发明公开
    BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION 审中-公开

    公开(公告)号：US20240088217A1

    公开(公告)日：2024-03-14

    申请号：US17940195

    申请日：2022-09-08

    Applicant: Intel Corporation

    Inventor： Tao Chu ,  Minwoo Jang ,  Chia-Ching Lin ,  Yanbin Luo ,  Ting-Hsiang Hung ,  Feng Zhang ,  Guowei Xu

    IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/7856

    Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

    INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT
    8.
    发明公开
    INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT 审中-公开

    公开(公告)号：US20240321887A1

    公开(公告)日：2024-09-26

    申请号：US18187801

    申请日：2023-03-22

    Applicant: Intel Corporation

    Inventor： Tao Chu ,  Yanbin Luo ,  Yusung Kim ,  Minwoo Jang ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Zheng Guo

    IPC: H01L27/092 ,  H01L29/49

    CPC classification number: H01L27/0922 ,  H01L29/4966

    Abstract: An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.

    INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT
    9.
    发明公开
    INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT 审中-公开

    公开(公告)号：US20240321859A1

    公开(公告)日：2024-09-26

    申请号：US18187782

    申请日：2023-03-22

    Applicant: Intel Corporation

    Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Anand S. Murthy ,  Tahir Ghani

    IPC: H01L27/02 ,  H01L27/088

    CPC classification number: H01L27/0207 ,  H01L27/088

    Abstract: An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.

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