公开(公告)号：US20250096114A1

公开(公告)日：2025-03-20

申请号：US18469810

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Robin Chao ,  Chiao-Ti Huang ,  Guowei Xu ,  Ting-Hsiang Hung ,  Tao Chu ,  Feng Zhang ,  Chia-Ching Lin ,  Yang Zhang ,  Anand Murthy ,  Conor P. Puls

IPC: H01L23/522 ,  H01L23/528

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

公开(公告)号：US20240321962A1

公开(公告)日：2024-09-26

申请号：US18187965

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Robin Chao ,  Guowei Xu ,  Feng Zhang ,  Minwoo Jang

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775

CPC classification number: H01L29/068 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/165 ,  H01L29/42392

Abstract: Described herein are nanoribbon-based transistor devices in which the nanoribbons have rounded cross-sections. The nanoribbons may include caps or outer layers of semiconductor channel material grown over an inner layer of semiconductor channel material. Different materials may be used for the outer layers of NMOS and PMOS transistors. In one example, an integrated circuit device includes NMOS transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon, and a PMOS transistors formed from or more nanoribbons with rounded cross-sections and an outer layer of silicon germanium.

公开(公告)号：US20250098249A1

公开(公告)日：2025-03-20

申请号：US18467859

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Avijit Barik ,  Tao Chu ,  Minwoo Jang ,  Tofizur RAHMAN ,  Conor P. Puls ,  Ariana E. Bondoc ,  Diane Lancaster ,  Chi-Hing Choi ,  Derek Keefer

IPC: H01L29/45 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

公开(公告)号：US20250087530A1

公开(公告)日：2025-03-13

申请号：US18463436

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Tao Chu ,  Guowei Xu ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Ting-Hsiang Hung ,  Anand Murthy

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.

公开(公告)号：US20240222484A1

公开(公告)日：2024-07-04

申请号：US18092152

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Chelsey Dorow ,  Kirby Maxey ,  Carl H. Naylor ,  Tao Chu ,  Guowei Xu ,  Uygar Avci ,  Feng Zhang ,  Ting-Hsiang Hung ,  Ande Kitamura ,  Mahmut Sami Kavrik

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.

公开(公告)号：US20240088217A1

公开(公告)日：2024-03-14

申请号：US17940195

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Chia-Ching Lin ,  Yanbin Luo ,  Ting-Hsiang Hung ,  Feng Zhang ,  Guowei Xu

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/7856

Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

公开(公告)号：US20250107156A1

公开(公告)日：2025-03-27

申请号：US18471710

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Robin Chao ,  Jaladhi Mehta ,  Tao Chu ,  Guowei Xu ,  Ting-Hsiang Hung ,  Feng Zhang ,  Yang Zhang ,  Chia-Ching Lin ,  Chung-Hsun Lin ,  Anand Murthy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

公开(公告)号：US20250089310A1

公开(公告)日：2025-03-13

申请号：US18466246

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Ting-Hsiang Hung ,  Yang Zhang ,  Robin Chao ,  Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Feng Zhang ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.

公开(公告)号：US20240321987A1

公开(公告)日：2024-09-26

申请号：US18187990

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Robin Chao ,  Chiao-Ti Huang ,  Feng Zhang ,  Minwoo Jang ,  Chia-Ching Lin ,  Biswajeet Guha ,  Yue Zhong ,  Anand S. Murthy

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.

公开(公告)号：US20240113118A1

公开(公告)日：2024-04-04

申请号：US17956188

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul A. Packan

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L27/0924

Abstract: Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.