公开(公告)号：US09836399B2

公开(公告)日：2017-12-05

申请号：US14671411

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin Aurangabadwala

IPC: G06F12/12 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/123 ,  G06F12/0804

CPC classification number: G06F12/0833 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/123 ,  G06F2212/1008

Abstract: A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.

公开(公告)号：US20160283380A1

公开(公告)日：2016-09-29

申请号：US14671411

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Krishna N. Vinod ,  Avinash Sodani ,  Zainulabedin Aurangabadwala

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/123 ,  G06F2212/1008

Abstract: A processor includes a processing core, an L1 cache, operatively coupled to the processing core, the L1 cache comprising an L1 cache entry to store a data item, an L2 cache, inclusive with respect to the L1 cache, the L2 cache comprising an L2 cache entry corresponding to the L1 cache entry, an activity flag associated with the L2 cache entry, the activity flag indicating an activity status of the L1 cache entry, and a cache controller to, in response to detecting an access operation with respect to the L1 cache entry, set the flag to an active status.

Abstract translation: 处理器包括可操作地耦合到所述处理核心的处理核心，L1高速缓存器，所述L1高速缓存器包括相对于所述L1高速缓存存储数据项的L1高速缓存条目，L2高速缓存，所述L2高速缓存包括L2 对应于L1高速缓存条目的缓存条目，与L2高速缓存条目相关联的活动标志，指示L1高速缓存条目的活动状态的活动标志，以及高速缓存控制器，响应于检测到关于L1的访问操作 缓存条目，将标志设置为活动状态。