公开(公告)号：US20240126681A1

公开(公告)日：2024-04-18

申请号：US18539350

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Zhiguo WEI ,  Yufu LI ,  Tao XU

IPC: G06F12/02

CPC classification number: G06F12/0223

Abstract: A method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. The first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. The external device and the first circuitry are configured with a specific data pattern. A data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. The data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. Data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.