公开(公告)号：US20250004878A1

公开(公告)日：2025-01-02

申请号：US18539380

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Yanxin ZHAO ,  Tao XU ,  Yufu LI ,  Shijie LIU ,  Lei ZHU

IPC: G06F11/10

Abstract: A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

公开(公告)号：US20240385754A1

公开(公告)日：2024-11-21

申请号：US18570674

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Daocheng BU ,  Dujian WU ,  Yufu LI ,  Vincent ZIMMER

IPC: G06F3/06

Abstract: Various examples relate to a control apparatus, a control device, a method, and a computer program for managing repair of a memory circuitry, and to a corresponding computing device. The control apparatus comprises processing circuitry configured to determine a score of a memory failure probability of at least one memory cell of the memory circuitry and trigger a repair procedure of the at least one memory cell of the memory circuitry when the score reaches a threshold.

公开(公告)号：US20240126681A1

公开(公告)日：2024-04-18

申请号：US18539350

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Zhiguo WEI ,  Yufu LI ,  Tao XU

IPC: G06F12/02

CPC classification number: G06F12/0223

Abstract: A method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. The first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. The external device and the first circuitry are configured with a specific data pattern. A data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. The data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. Data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.

公开(公告)号：US20230289303A1

公开(公告)日：2023-09-14

申请号：US18040944

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Shijie LIU ,  Tao XU ,  Lei ZHU ,  Yufu LI

IPC: G06F13/16 ,  G06F13/10 ,  G06F13/42

CPC classification number: G06F13/1652 ,  G06F13/102 ,  G06F13/4221

Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.