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    Method and system for error check and scrub error data collection and reporting for a memory device
    1.
    发明申请
    Method and system for error check and scrub error data collection and reporting for a memory device 有权

    公开(公告)号：US20250004878A1

    公开(公告)日：2025-01-02

    申请号：US18539380

    申请日：2023-12-14

    Applicant: Intel Corporation

    Inventor： Yanxin ZHAO ,  Tao XU ,  Yufu LI ,  Shijie LIU ,  Lei ZHU

    IPC: G06F11/10

    Abstract: A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

    ACCELERATING SYSTEM BOOT TIMES VIA HOST-MANAGED DEVICE MEMORY
    2.
    发明公开
    ACCELERATING SYSTEM BOOT TIMES VIA HOST-MANAGED DEVICE MEMORY 审中-公开

    公开(公告)号：US20230176735A1

    公开(公告)日：2023-06-08

    申请号：US17997030

    申请日：2020-05-22

    Applicant: INTEL CORPORATION

    Inventor： Keivin Yufu LI ,  Zhenfu CHAI ,  Lei ZHU ,  Junjie HE ,  Shijie LIU ,  Tao XU

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0673 ,  G06F3/0632

    Abstract: Systems, apparatuses and methods may provide for technology that initializes a host-managed device memory (HDM) as a temporary proxy for a system memory, wherein the HDM is associated with an accelerator. The technology also creates a shadow copy of boot firmware code in the HDM and executes one or more boot instructions in the shadow copy of the boot firmware code. In one example, the one or more boot instructions are to be one or more of executed before an initialization of the system memory or executed in parallel with the initialization of the system memory.

    RUNTIME CELL ROW REPLACEMENT IN A MEMORY
    4.
    发明申请
    RUNTIME CELL ROW REPLACEMENT IN A MEMORY 有权

    公开(公告)号：US20210191829A1

    公开(公告)日：2021-06-24

    申请号：US17262696

    申请日：2018-09-15

    Applicant: INTEL CORPORATION

    Inventor： Satish MUTHIYALU ,  Yingwen CHEN ,  Yu YU ,  Tao XU

    IPC: G06F11/20 ,  G06F13/24

    Abstract: Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.

    Method and system for dynamically detecting memory sub-channel mapping and data lane mapping between a memory controller and physical layer circuitry
    5.
    发明公开
    Method and system for dynamically detecting memory sub-channel mapping and data lane mapping between a memory controller and physical layer circuitry 审中-公开

    公开(公告)号：US20240126681A1

    公开(公告)日：2024-04-18

    申请号：US18539350

    申请日：2023-12-14

    Applicant: Intel Corporation

    Inventor： Zhiguo WEI ,  Yufu LI ,  Tao XU

    IPC: G06F12/02

    CPC classification number: G06F12/0223

    Abstract: A method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. The first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. The external device and the first circuitry are configured with a specific data pattern. A data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. The data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. Data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.

    IMPROVING REMOTE TRAFFIC PERFORMANCE ON CLUSTER-AWARE PROCESSORS
    6.
    发明公开
    IMPROVING REMOTE TRAFFIC PERFORMANCE ON CLUSTER-AWARE PROCESSORS 审中-公开

    公开(公告)号：US20230289303A1

    公开(公告)日：2023-09-14

    申请号：US18040944

    申请日：2020-09-18

    Applicant: Intel Corporation

    Inventor： Shijie LIU ,  Tao XU ,  Lei ZHU ,  Yufu LI

    IPC: G06F13/16 ,  G06F13/10 ,  G06F13/42

    CPC classification number: G06F13/1652 ,  G06F13/102 ,  G06F13/4221

    Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.

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