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公开(公告)号：US10651857B2
公开(公告)日：2020-05-12
申请号：US15194999
申请日：2016-06-28
Applicant: Intel IP Corporation
Inventor： Andreas Roithmeier , Thomas Gustedt , Herwig Dietl-Steinmaurer , Christian Wicpalek
Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.
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公开(公告)号：US20170373694A1
公开(公告)日：2017-12-28
申请号：US15194999
申请日：2016-06-28
Applicant: Intel IP Corporation
Inventor： Andreas Roithmeier , Thomas Gustedt , Herwig Dietl-Steinmaurer , Christian Wicpalek
IPC: H03L7/083
CPC classification number: H03L7/083 , H03L7/0802 , H03L7/099 , H03L2207/06
Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator
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