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    PHASE TRACKER FOR A PHASE LOCKED LOOP
    3.
    发明申请
    PHASE TRACKER FOR A PHASE LOCKED LOOP 有权
    相位锁相环的相位跟踪器

    公开(公告)号：US20160087639A1

    公开(公告)日：2016-03-24

    申请号：US14494718

    申请日：2014-09-24

    Applicant: Intel IP Corporation

    Inventor： Christian Wicpalek ,  Thomas Mayer ,  Andreas Mayer ,  Thorsten Tracht

    IPC: H03L7/085 ,  G04F10/00

    CPC classification number: H03L7/085 ,  G04F10/005 ,  H03L7/1976

    Abstract: A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

    Abstract translation: 锁相环包括接收具有参考频率的参考信号的前馈路径，并输出具有作为参考信号和反馈信号的函数的输出频率的输出信号。 锁相环还包括具有与其相关联的分频器电路的反馈路径，其被配置为接收输出信号并且基于分频器电路的除法产生具有降低的频率的反馈信号。 反馈信号被提供给前馈路径。 锁相环还包括配置成接收调制数据并将分频器控制信号提供给分频器电路以控制其分频值的调制器电路，以及相位跟踪器电路，被配置为从相位漂移的初始相位值 该输出信号由于锁相环中的锁定状态而中断。

    Phase tracker for a phase locked loop
    4.
    发明授权
    Phase tracker for a phase locked loop 有权
    相位跟踪器用于锁相环

    公开(公告)号：US09584139B2

    公开(公告)日：2017-02-28

    申请号：US14494718

    申请日：2014-09-24

    Applicant: Intel IP Corporation

    Inventor： Christian Wicpalek ,  Thomas Mayer ,  Andreas Mayer ,  Thorsten Tracht

    IPC: H03L7/08 ,  H03L7/085 ,  G04F10/00 ,  H03L7/197

    CPC classification number: H03L7/085 ,  G04F10/005 ,  H03L7/1976

    Abstract: A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

    Abstract translation: 锁相环包括接收具有参考频率的参考信号的前馈路径，并输出具有作为参考信号和反馈信号的函数的输出频率的输出信号。 锁相环还包括具有与其相关联的分频器电路的反馈路径，其被配置为接收输出信号并且基于分频器电路的除法产生具有降低的频率的反馈信号。 反馈信号被提供给前馈路径。 锁相环还包括配置成接收调制数据并将分频器控制信号提供给分频器电路以控制其分频值的调制器电路，以及相位跟踪器电路，被配置为从相位漂移的初始相位值 该输出信号由于锁相环中的锁定状态而中断。

    Coarse tuning selection for phase locked loops
    5.
    发明授权
    Coarse tuning selection for phase locked loops 有权
    用于锁相环的粗调整选择

    公开(公告)号：US09548746B2

    公开(公告)日：2017-01-17

    申请号：US14578773

    申请日：2014-12-22

    Applicant: Intel IP Corporation

    Inventor： Christian Wicpalek ,  Herwig Dietl-Steinmaurer

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/085 ,  H04L7/033 ,  H03L7/10

    CPC classification number: H03L7/099 ,  H03L7/085 ,  H03L7/104 ,  H03L2207/06 ,  H04L7/033

    Abstract: A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine tuning operations. The system operates to calibrate the coarse tuning of the oscillator based on one or more characteristics related to the oscillator and determined by a characterization component, an interpolation function and one or more final measurements. An adjustment component is configured to adjust the coarse tuning value based on at least one final frequency measurement to generate a final coarse tuning value and set the coarse tuning of the oscillator based on the final coarse tuning value.

    Abstract translation: 锁相环系统包括锁相环和根据粗调调和微调操作进行粗调和微调的振荡器。 该系统用于基于与振荡器相关的一个或多个特性来校准振荡器的粗调，并且由特征分量，内插函数和一个或多个最终测量确定。 调整组件被配置为基于至少一个最终频率测量来调整粗调调整值，以产生最终粗调谐值，并且基于最终粗调谐值来设置振荡器的粗调。

    COARSE TUNING SELECTION FOR PHASE LOCKED LOOPS
    6.
    发明申请
    COARSE TUNING SELECTION FOR PHASE LOCKED LOOPS 有权
    用于相位锁定的声音调谐选择

    公开(公告)号：US20160182065A1

    公开(公告)日：2016-06-23

    申请号：US14578773

    申请日：2014-12-22

    Applicant: Intel IP Corporation

    Inventor： Christian Wicpalek ,  Herwig Dietl-Steinmaurer

    IPC: H03L7/099 ,  H04L7/033 ,  H03L7/085

    CPC classification number: H03L7/099 ,  H03L7/085 ,  H03L7/104 ,  H03L2207/06 ,  H04L7/033

    Abstract: A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine tuning operations. The system operates to calibrate the coarse tuning of the oscillator based on one or more characteristics related to the oscillator and determined by a characterization component, an interpolation function and one or more final measurements. An adjustment component is configured to adjust the coarse tuning value based on at least one final frequency measurement to generate a final coarse tuning value and set the coarse tuning of the oscillator based on the final coarse tuning value

    Abstract translation: 锁相环系统包括锁相环和根据粗调调和微调操作进行粗调和微调的振荡器。 该系统用于基于与振荡器相关的一个或多个特性来校准振荡器的粗调，并且由特征分量，内插函数和一个或多个最终测量确定。 调整组件被配置为基于至少一个最终频率测量来调整粗调调整值以产生最终粗调谐值，并且基于最终粗调谐值来设置振荡器的粗调

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