公开(公告)号：US11120192B1

公开(公告)日：2021-09-14

申请号：US16853180

申请日：2020-04-20

Applicant: International Business Machines Corporation

Inventor： Hua Xiang ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jennifer Kazda

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/12

Abstract: A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

公开(公告)号：US20200057835A1

公开(公告)日：2020-02-20

申请号：US16664899

申请日：2019-10-27

Applicant: International Business Machines Corporation

Inventor： Diwesh Pandey ,  Christian Schulte ,  Gustavo E. Tellez

IPC: G06F17/50

Abstract: A global router determines edge capacity of global tiles for a first integrated circuit in a global routing operation. The global router determines a respective edge capacity of first width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit in a first global routing operation. The global router determines a respective edge capacity of second width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit in a second global routing operation. The edge capacities for first width and second width wire tracks are determined in separate operations by the global router as part of the operations performed for fabrication of the first integrated circuit.

公开(公告)号：US20180285507A1

公开(公告)日：2018-10-04

申请号：US15477549

申请日：2017-04-03

Applicant: International Business Machines Corporation

Inventor： Michael A. Kazda ,  Diwesh Pandey ,  Sven Peyer ,  Gustavo E. Tellez

IPC: G06F17/50 ,  H03K19/177

Abstract: A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

公开(公告)号：US09158885B1

公开(公告)日：2015-10-13

申请号：US14278974

申请日：2014-05-15

Applicant: International Business Machines Corporation

Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Alexander Ivrii ,  Lars W. Liebmann ,  Kevin W. McCullen ,  Gustavo E. Tellez ,  Michael Gester

IPC: G06F17/50

CPC classification number: G03F7/70433

Abstract: Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.

Abstract translation: 本公开的方法可以包括：使用计算设备来执行动作，包括：对所提出的集成电路（IC）布局应用设计规则检查（DRC），其中DRC应用一组限制性设计规则（RDR）作为响应 所提出的IC布局是接触区域（CA）布局; 响应于IC布局中的一个是金属层布局并且满足RDR集合来计算所提出的IC布局的冲突图; 确定IC布局是否是不可着色，不确定，部分可着色和完全可着色的; 并且部分地着色IC布局并且响应于IC布局是不确定的或部分可着色的而识别不可着色节点。

公开(公告)号：US10726187B2

公开(公告)日：2020-07-28

申请号：US16143697

申请日：2018-09-27

Applicant: International Business Machines Corporation

Inventor： Diwesh Pandey ,  Gustavo E. Tellez ,  Shaodi Gao

IPC: G06F30/00 ,  G06F30/394 ,  G06F30/398 ,  G06F119/18

Abstract: A method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning includes generating an initial routing result that indicates a location and length of connections between components, and generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes. The method also includes subdividing the initial constraint graph into two or more subgraphs, determining a final position of each of the nodes in the two or more subgraphs, and generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections. The routed design is provided for manufacture of the integrated circuit.

公开(公告)号：US20190138683A1

公开(公告)日：2019-05-09

申请号：US16240719

申请日：2019-01-05

Applicant: International Business Machines Corporation

Inventor： Diwesh Pandey ,  Christian Schulte ,  Gustavo E. Tellez

IPC: G06F17/50

Abstract: A global router determines edge capacity of global tiles for a first integrated circuit in a global routing operation. The global router determines a respective edge capacity of minimum width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit. Next, the global router determines a respective edge capacity of non-minimum width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit. The edge capacities for minimum width and non-minimum width wire tracks are determined in separate operations within the global routing operation for fabrication of an integrated circuit.

公开(公告)号：US09245076B2

公开(公告)日：2016-01-26

申请号：US13908562

申请日：2013-06-03

Applicant: International Business Machines Corporation

Inventor： Vassilios Gerousis ,  Lars W. Liebmann ,  Stefanus Mantik ,  Gustavo E. Tellez ,  Shuo Zhang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance.

Abstract translation: 各种实施例包括计算机实现的方法，计算机程序产品和用于对准集成电路（IC）布局中的一组正交电路元件的系统。 在一些实施例中，用于对准IC布局中的一组正交电路元件的计算机实现的方法包括：将所述一组正交电路元件中的每个正交电路元件分类为包括第一空间指定边缘和第二空间指定边缘 ; 并且根据所述第一空间指定边缘和所述第二空间指定边缘，将边缘布置格栅上的每个正交电路元件对准，所述边缘布置网格具有由第一距离分隔的第一组空间指定网格线， 一组间隔指定的网格线分开第二距离，其中第一组空格指定的网格线与第二组空格指定的网格线分开一个偏移距离。

公开(公告)号：US20190278873A1

公开(公告)日：2019-09-12

申请号：US16423242

申请日：2019-05-28

Applicant: International Business Machines Corporation

Inventor： Ying Zhou ,  Stephen T. Quay ,  Lakshmi N. Reddy ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jiang Hu

IPC: G06F17/50

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

公开(公告)号：US10372837B2

公开(公告)日：2019-08-06

申请号：US15896176

申请日：2018-02-14

Applicant: International Business Machines Corporation

Inventor： Ying Zhou ,  Stephen T. Quay ,  Lakshmi N. Reddy ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jiang Hu

IPC: G06F17/50

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

公开(公告)号：US20180373815A1

公开(公告)日：2018-12-27

申请号：US15896176

申请日：2018-02-14

Applicant: International Business Machines Corporation

Inventor： Ying Zhou ,  Stephen T. Quay ,  Lakshmi N. Reddy ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jiang Hu

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/84

Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.