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公开(公告)号：US09740589B2
公开(公告)日：2017-08-22
申请号：US14792964
申请日：2015-07-07
CPC分类号： G06F11/3495 , G06F11/00 , G06F11/3003 , G06F11/3461
摘要： A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.
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公开(公告)号：US10984159B1
公开(公告)日：2021-04-20
申请号：US16870994
申请日：2020-05-10
发明人： Ziv Nevo , Alexander Ivrii , Avi Ziv , Raviv Gal , Haim Kermany
IPC分类号： G06F30/33 , G06F30/398 , G06F11/263 , G06F11/26 , G06F11/36
摘要： A method, and apparatus and a computer program product for determining coverage in hardware verification based on relations between coverage events. The method comprises generating an over-approximation model of the hardware being verified to perform formal verification thereof with respect to a target coverage event being utilized in the verification process along with a set of coverage events. A score indicating an estimated conditional probability to hit the target coverage event in the verification process, given that the coverage event is hit in the verification process, may be determined for each coverage event based on the formal verification. The method further comprises selecting test suits to be executed in the verification process based on the scores and the test suits probability to hit each coverage event. The verification process may be the performed the selected test suits in order to cover the target coverage event.
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公开(公告)号：US10789403B1
公开(公告)日：2020-09-29
申请号：US16411193
申请日：2019-05-14
IPC分类号： G06F30/327 , G06F9/50 , G06F17/16
摘要： Embodiments of the invention are directed to a computer-implemented method of logic verification. The method includes obtaining a netlist of a circuit comprising a plurality of observable gates. A first observable gate is grouped together with a second observable gate based on a portion of a fan-in logic of the first observable gate being equal to a portion of a fan-in logic of the second observable gate. The group is expanded by including a third observable gate, based on a first strongly connected component (SCC) in the group having a similarity greater than a first threshold to a second SCC in the fan-in logic of the third observable gate. The group is further expanded by including a fourth observable gate, based on the distance of a portion of the fan-in logic of the fourth observable gate from a fan-in logic of at least one observable gate in the group of observable gates.
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公开(公告)号：US20170323044A1
公开(公告)日：2017-11-09
申请号：US15145543
申请日：2016-05-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.
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公开(公告)号：US09158885B1
公开(公告)日：2015-10-13
申请号：US14278974
申请日：2014-05-15
发明人： Michael S. Gray , Matthew T. Guzowski , Alexander Ivrii , Lars W. Liebmann , Kevin W. McCullen , Gustavo E. Tellez , Michael Gester
IPC分类号： G06F17/50
CPC分类号： G03F7/70433
摘要： Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.
摘要翻译： 本公开的方法可以包括：使用计算设备来执行动作，包括：对所提出的集成电路（IC）布局应用设计规则检查（DRC），其中DRC应用一组限制性设计规则（RDR）作为响应 所提出的IC布局是接触区域（CA）布局; 响应于IC布局中的一个是金属层布局并且满足RDR集合来计算所提出的IC布局的冲突图; 确定IC布局是否是不可着色，不确定，部分可着色和完全可着色的; 并且部分地着色IC布局并且响应于IC布局是不确定的或部分可着色的而识别不可着色节点。
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公开(公告)号：US11922130B2
公开(公告)日：2024-03-05
申请号：US17547413
申请日：2021-12-10
摘要： In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.
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公开(公告)号：US20170323043A1
公开(公告)日：2017-11-09
申请号：US15145406
申请日：2016-05-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.
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8.发明申请LIFTING OF BOUNDED LIVENESS COUNTEREXAMPLES TO CONCRETE LIVENESS COUNTEREXAMPLES 有权提升生活环境的生活对象混合生活对策公开(公告)号：US20170010949A1
公开(公告)日：2017-01-12
申请号：US14792964
申请日：2015-07-07
CPC分类号： G06F11/3495 , G06F11/00 , G06F11/3003 , G06F11/3461
摘要： A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.
摘要翻译： 通过一个或多个处理器接收系统组件的有界活动失败的痕迹，以及公平约束和活动断言条件。 一个或多个处理器为未分配的输入值和跟踪的寄存器值产生随机值，并且模拟轨迹状态序列中的每一个的遍历。 一个或多个处理器确定是否遍历迹线的状态序列导致状态的重复，并且响应于确定遍历迹线的状态序列确实导致状态的重复，以及一组公平约束 在状态的重复中被断言，并且在整个状态的重复中保持连续的活动断言条件，报告系统组件的活跃性的具体反例。
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公开(公告)号：US10540469B2
公开(公告)日：2020-01-21
申请号：US15844668
申请日：2017-12-18
发明人： Alexander Ivrii , Haim Kermany , Ziv Nevo
IPC分类号： G06F17/50
摘要： A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware design model configured to receive a startup state and send digital output values. Hardware processor(s) are used for generating a plurality of initial states. Hardware processor(s) are used for computing, using each one of the first and second hardware design models, at least one specific output value for each one of the plurality of initial states. Hardware processor(s) are used for selecting corresponding initial states that produce equivalent at least one specific output value between the first hardware design model and the second hardware design model. Hardware processor(s) are used for storing the selected corresponding initial states as mappings between the first hardware design model and the second hardware design model.
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公开(公告)号：US20200019653A1
公开(公告)日：2020-01-16
申请号：US16032786
申请日：2018-07-11
发明人： Raj Kumar Gajavelly , Jason R. Baumgartner , Robert L. Kanzelman , Alexander Ivrii , Pradeep Kumar Nalla
IPC分类号： G06F17/50
摘要： A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.
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