摘要:
A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要:
A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.