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    COMPLETION MECHANISM FOR A MICROPROCESSOR INSTRUCTION COMPLETION TABLE
    1.
    发明申请
    COMPLETION MECHANISM FOR A MICROPROCESSOR INSTRUCTION COMPLETION TABLE 审中-公开

    公开(公告)号：US20200065102A1

    公开(公告)日：2020-02-27

    申请号：US16109952

    申请日：2018-08-23

    申请人： International Business Machines Corporation

    发明人： Kenneth L. WARD ,  Susan E. EISEN ,  Dung Q. NGUYEN ,  Glenn O. KINCAID ,  Joe LEE ,  Deepak K. SINGH

    IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F9/30

    摘要： Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

    INSTRUCTION COMPLETION TABLE CONTAINING ENTRIES THAT SHARE INSTRUCTION TAGS
    3.
    发明申请
    INSTRUCTION COMPLETION TABLE CONTAINING ENTRIES THAT SHARE INSTRUCTION TAGS 审中-公开

    公开(公告)号：US20200026521A1

    公开(公告)日：2020-01-23

    申请号：US16039848

    申请日：2018-07-19

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Kenneth L. WARD ,  Dung Q. NGUYEN ,  Hung LE ,  Susan E. EISEN

    IPC分类号： G06F9/38

    摘要： Systems, methods, and computer-readable media are described for performing instruction execution using an instruction completion table (ICT) that is configured to accommodate shared ICT entries. A shared ICT entry maps to multiple instructions such as, for example, two instructions. Each shared ICT entry may be referenced by an even instruction tag (ITAG) and an odd ITAG that correspond to respective instructions that have been grouped together in the shared ICT entry. The instructions corresponding to a given shared ICT entry can be executed and finished independently of one another. A shared ICT entry is completed when each execution of each instruction corresponding to the shared ICT entry has finished and when all prior ICT entries have completed. Also described herein are system, methods, and computer-readable media for flushing instructions in shared ICT entries in response to execution of a branch instruction.

    MECHANISM TO STOP COMPLETIONS USING STOP CODES IN AN INSTRUCTION COMPLETION TABLE
    4.
    发明申请
    MECHANISM TO STOP COMPLETIONS USING STOP CODES IN AN INSTRUCTION COMPLETION TABLE 审中-公开

    公开(公告)号：US20200065110A1

    公开(公告)日：2020-02-27

    申请号：US16110178

    申请日：2018-08-23

    申请人： International Business Machines Corporation

    发明人： Kenneth L. WARD ,  Dung Q. NGUYEN ,  Susan E. EISEN ,  Christopher M. MUELLER ,  Joe LEE ,  Deepak K. SINGH

    IPC分类号： G06F9/38

    摘要： Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.

    SPECULATIVE EXECUTION OF BOTH PATHS OF A WEAKLY PREDICTED BRANCH INSTRUCTION
    6.
    发明申请
    SPECULATIVE EXECUTION OF BOTH PATHS OF A WEAKLY PREDICTED BRANCH INSTRUCTION 审中-公开

    公开(公告)号：US20200026520A1

    公开(公告)日：2020-01-23

    申请号：US16039857

    申请日：2018-07-19

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Kenneth L. WARD ,  Dung Q. NGUYEN ,  Susan E. EISEN ,  Hung LE

    IPC分类号： G06F9/38

    摘要： Systems, methods, and computer-readable media are described for performing speculative execution of both paths/branches of a weakly predicted branch instruction. A branch instruction may be fetched from an instruction queue and determined to be a weakly predicted branch instruction, in which case, both paths of the branch instruction may be dispatched and speculatively executed. When the actual path taken becomes known, instructions corresponding to the path not taken may be flushed. Instructions from both paths of a weakly predicted branch instruction that are speculatively executed may be dispatch and executed in an interleaved manner.