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公开(公告)号：US20190034666A1
公开(公告)日：2019-01-31
申请号：US15661048
申请日：2017-07-27
发明人： Richard H. Boivie , Bradly G. Frey , William E. Hall , Benjamin Herrenschmidt , Guerney D. H. Hunt , Jentje Leenstra , Paul Mackerras , Cathy May , Albert J. Van Norstrand, JR.
CPC分类号： G06F21/74 , G06F9/45558 , G06F21/53 , G06F2009/45587 , G06F2221/2143 , G06F2221/2149
摘要： Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.
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公开(公告)号：US20150378770A1
公开(公告)日：2015-12-31
申请号：US14727245
申请日：2015-06-01
发明人： Guy L. Guthrie , Naresh Nayar , Geraint North , William J. Starke , Albert J. Van Norstrand, JR.
CPC分类号： G06F9/45558 , G06F11/14 , G06F11/141 , G06F11/1438 , G06F11/1458 , G06F11/1484 , G06F11/203 , G06F11/2035 , G06F11/2046 , G06F11/2097 , G06F12/08 , G06F12/0804 , G06F12/0806 , G06F12/0833 , G06F12/0855 , G06F12/128 , G06F2009/45583 , G06F2201/86 , G06F2212/151 , G06F2212/62 , G06F2212/621
摘要： A virtual machine backup method includes utilizing a log to indicate updates to memory of a virtual machine when the updates are evicted from a cache of the virtual machine. A guard band is determined that indicates a threshold amount of free space for the log. A determination is made that the guard band will be or has been encroached upon corresponding to indicating an update in the log. A backup image of the virtual machine is updated based, at least in part, on a set of one or more entries of the log, wherein the set of entries is sufficient to comply with the guard band. The set of entries is removed from the log.
摘要翻译： 虚拟机备份方法包括当更新从虚拟机的高速缓存中逐出时利用日志指示对虚拟机的存储器的更新。 确定指示日志的可用空间的阈值量的保护带。 确定保护频段将被或被侵占对应于指示日志中的更新。 至少部分地基于日志的一个或多个条目来更新虚拟机的备份映像，其中该组条目足以符合保护带。 从日志中删除一组条目。
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公开(公告)号：US20150143055A1
公开(公告)日：2015-05-21
申请号：US14548624
申请日：2014-11-20
发明人： Guy L. Guthrie , Naresh Nayar , Geraint North , William J. Starke , Albert J. Van Norstrand, JR.
CPC分类号： G06F9/45558 , G06F11/14 , G06F11/141 , G06F11/1438 , G06F11/1458 , G06F11/1484 , G06F11/203 , G06F11/2035 , G06F11/2046 , G06F11/2097 , G06F12/08 , G06F12/0804 , G06F12/0806 , G06F12/0833 , G06F12/0855 , G06F12/128 , G06F2009/45583 , G06F2201/86 , G06F2212/151 , G06F2212/62 , G06F2212/621
摘要： A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines, a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, periodically check the image modification flags and write only the memory address of the flagged cache rows in the defined log. The processor unit is further arranged to monitor the free space available in the defined log and to trigger an interrupt if the free space available falls below a specific amount.
摘要翻译： 计算机系统包括处理器单元，其被配置为运行运行一个或多个虚拟机的管理程序，连接到处理器单元并包括多个高速缓存行的高速缓存，每个高速缓存行包括存储器地址，高速缓存行和图像修改标志 以及连接到高速缓存并被布置成存储至少一个虚拟机的图像的存储器。 处理器单元被布置为在存储器中定义日志，并且高速缓存还包括高速缓存控制器，其被布置为设置由被备份的虚拟机修改的高速缓存行的映像修改标志，周期性地检查映像修改标志，并且仅写入 定义的日志中标记的缓存行的内存地址。 处理器单元还被布置成监视定义的日志中可用的可用空间，并且如果可用空间低于特定量，则触发中断。
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4.发明申请公开(公告)号：US20180121205A1
公开(公告)日：2018-05-03
申请号：US15693387
申请日：2017-08-31
发明人： Maarten J. Boersma , Robert A. Cordes , David A. Hrusecky , Jennifer L. Molnar , Brian W. Thompto , Albert J. Van Norstrand, JR. , Kenneth L. Ward
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/3802 , G06F9/3836 , G06F9/3851 , G06F9/524 , G06F12/0875 , G06F2212/452
摘要： An instruction sequencing unit in an out-of-order (OOO) processor includes a Most Favored Instruction (MFI) mechanism that designates an instruction as an MFI. The processing queues in the processor identify when they contain the MFI, and assures processing the MFI. The MFI remains the MFI until it is completed or is flushed, and which time the MFI mechanism selects the next MFI.
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5.发明申请公开(公告)号：US20190187992A1
公开(公告)日：2019-06-20
申请号：US15843982
申请日：2017-12-15
发明人： Kenneth L. WARD , Susan E. EISEN , Dung Q. NGUYEN , Albert J. Van Norstrand, JR. , Glenn O. KINCAID , Christopher M. MUELLER
CPC分类号： G06F9/3851 , G06F9/4818
摘要： Implementations are disclosed for a simultaneous multithreading processor configured to execute a plurality of threads. In one implementation, the simultaneous multithreading processor is configured to select a first thread of the plurality of threads according to a predefined scheme, and access an instruction completion table to determine whether the first thread is eligible to have a first instruction prioritized. Responsive to determining that the first thread is eligible to have the first instruction prioritized, the simultaneous multithreading processor is further configured to execute the first instruction of the first thread using a dedicated prioritization resource.
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公开(公告)号：US20220066830A1
公开(公告)日：2022-03-03
申请号：US17004573
申请日：2020-08-27
发明人： Steven J. Battle , Dung Q. Nguyen , Albert J. Van Norstrand, JR. , Tu-An T. Nguyen , Cliff Kucharski
IPC分类号： G06F9/50 , G06F16/178
摘要： Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.
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公开(公告)号：US20200019405A1
公开(公告)日：2020-01-16
申请号：US16035676
申请日：2018-07-15
发明人： Steven J. Battle , Joshua W. Bowman , Dung Q. Nguyen , Albert J. Van Norstrand, JR. , Cliff Kucharski , Hung Q. Le , Brian D. Barrick
IPC分类号： G06F9/38 , G06F9/46 , G06F9/30 , G06F12/0897
摘要： A split level history buffer in a central processing unit is provided. The history buffer includes first, second, and third levels, each having different characteristics. Operational instructions are provided to support the split history buffer. A first instruction is fetched, tagged, and stored in an entry of a register file. As a second instruction is fetched and tagged, the first instruction is evicted from the register file and stored in the first level of the history buffer. Similarly, as a result for the first instruction is generated, the first instruction and the generated result are stored in the second level of the history buffer. In response to instruction completion, instead of remaining in the second level, the first instruction, which contains pre-transactional memory checkpoint data, is moved from the second level to the third level of the history buffer, together with pre-transactional memory data, and the first instruction entry in the second level is invalidated.
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