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公开(公告)号：US11314511B2
公开(公告)日：2022-04-26
申请号：US15816401
申请日：2017-11-17
摘要： A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.
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公开(公告)号：US11132290B2
公开(公告)日：2021-09-28
申请号：US16429291
申请日：2019-06-03
发明人： Michael K. Gschwind
IPC分类号： G06F12/00 , G06F12/02 , G06F13/16 , G06F12/1045
摘要： Processing within a non-uniform memory access (NUMA) computing environment is facilitated by obtaining memory for a memory heap for an application of a virtualized environment of the NUMA computing environment, and assigning portions of memory of the obtained memory to locality domain-based freelists. The assigning including obtaining, for a selected portion of memory of the portions of memory, a locality domain within the NUMA computing environment with which the portion of memory is associated, and adding the selected portion of memory to a corresponding locality domain-based freelist of the locality domain-based freelists based on the associated locality domain of the portion of memory. Domain locality is then used in allocating the memory from the locality domain-based freelists to processors of the NUMA computing environment performing processing of the application.
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公开(公告)号：US11080052B2
公开(公告)日：2021-08-03
申请号：US16668527
申请日：2019-10-30
发明人： Michael K. Gschwind , Christian Jacobi , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F12/0875 , G06F9/38
摘要： Effectiveness of prefetch instructions is determined. A prefetch instruction is executed to request that data be fetched into a cache of the computing environment. The effectiveness of the prefetch instruction is determined. This includes updating, based on executing the prefetch instruction, a cache directory of the cache. The updating includes, in the cache directory, effectiveness data relating to the data. The effectiveness data includes whether the data was installed in the cache based on the prefetch instruction. Additionally, the determining the effectiveness includes obtaining at least a portion of the effectiveness data from the cache directory, and using the at least a portion of effectiveness data to determine the effectiveness of the prefetch instruction.
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公开(公告)号：US11016744B2
公开(公告)日：2021-05-25
申请号：US16538990
申请日：2019-08-13
发明人： Michael K. Gschwind
摘要： Optimizations are provided for sibling calls. A sibling caller is marked to indicate that it may call a sibling routine or that it may call an external sibling routine. Based on the marking, certain processing is performed to facilitate use of sibling calls, particularly when the sibling routine being called is external to the caller.
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公开(公告)号：US10936314B2
公开(公告)日：2021-03-02
申请号：US16379298
申请日：2019-04-09
摘要： Branch prediction is suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions.
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公开(公告)号：US10901738B2
公开(公告)日：2021-01-26
申请号：US15811982
申请日：2017-11-14
摘要： Bulk store and load operations of configuration state registers. An instruction to perform a bulk operation for a group of configuration state registers having a common characteristic is executed. To perform the bulk operation for the group of configuration state registers, a plurality of operations is performed, and based on performing the plurality of operations, the instruction is completed.
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7.发明授权公开(公告)号：US10782979B2
公开(公告)日：2020-09-22
申请号：US15489846
申请日：2017-04-18
摘要： A reload multiple instruction is used to restore a set of architected registers saved by a spill multiple instruction. The reload multiple instruction is executed, and the executing includes determining the set of architected registers to be restored, which is specified by the reload multiple instruction. The set of architected registers is restored from a selected snapshot that maps architected registers to physical registers. The restoring replaces one or more physical registers currently assigned to one or more architected registers of the set of architected registers with one or more physical registers of the selected snapshot corresponding to the set of architected registers.
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公开(公告)号：US10768931B2
公开(公告)日：2020-09-08
申请号：US15812529
申请日：2017-11-14
摘要： Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.
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公开(公告)号：US10761852B2
公开(公告)日：2020-09-01
申请号：US14871959
申请日：2015-09-30
摘要： Addressability of instructions and the addressing of data ranges are extended. One or more operands obtained from fields explicitly specified by an instruction are overridden (i.e., ignored), and instead, an address based on the instruction (e.g., an instruction address) is substituted for the one or more operands. This provides an address having more bits than allowed by the operand being overridden, thereby extending addressability of the instruction and extended data range addressing. Further, in one aspect, additional bits may be added to one or more immediate fields of the instruction, thereby extending addressability of the instructions and extending data range addressing.
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公开(公告)号：US10747533B2
公开(公告)日：2020-08-18
申请号：US16401134
申请日：2019-05-02
发明人： Michael K. Gschwind
摘要： An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
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