-
公开(公告)号：US20240320033A1
公开(公告)日：2024-09-26
申请号：US18187172
申请日：2023-03-21
CPC分类号： G06F9/4881 , G06F9/30036 , G06F9/3555
摘要： Solving linear systems by sending matrix data from a first computer to a second computer, directing the second computer in determining a solution to a parallel computing task for the matrix data, receiving the solution by the first computer, determining a solution to a non-parallel computing task for the matrix data using the first computer, and providing the solution to the non-parallel computing task.
-
公开(公告)号：US20220366005A1
公开(公告)日：2022-11-17
申请号：US17245801
申请日：2021-04-30
发明人： Tomasz J. Nowicki , Oguzhan Murat Onen , Tayfun Gokmen , Vasileios Kalantzis , Chai Wah Wu , Mark S. Squillante , Malte Johannes Rasch , Wilfried Haensch , Lior Horesh
摘要： Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.
-
公开(公告)号：US20240193448A1
公开(公告)日：2024-06-13
申请号：US18193082
申请日：2023-03-30
发明人： Ismail Yunus Akhalwaya , Kenneth Clarkson , Lior Horesh , Mark Squillante , Shashanka Ubaru , Vasileios Kalantzis
摘要： Techniques and a system to facilitate estimation of a quantum phase, and more specifically, to facilitate estimation of an expectation value of a quantum state, by utilizing a hybrid of quantum and classical methods are provided. In one example, a system is provided. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include an encoding component and a learning component. The encoding component can encode an expectation value associated with a quantum state. The learning component can utilize stochastic inference to determine the expectation value based on an uncollapsed eigenvalue pair.
-
公开(公告)号：US20240020564A1
公开(公告)日：2024-01-18
申请号：US17863508
申请日：2022-07-13
发明人： Shashanka Ubaru , Kenneth Lee Clarkson , Ismail Yunus Akhalwaya , Mark S. Squillante , Vasileios Kalantzis , Lior Horesh
摘要： Systems and methods for operating a quantum system are described. A controller of a quantum system can generate a command signal. The quantum system can include quantum hardware having a plurality of qubits. An interface of the quantum system can control the quantum hardware based on the command signal to generate a random state vector represented by the plurality of qubits. The random state vector can include a specific number of independent entries. The interface can control the quantum hardware to determine moments of a matrix based on the random state vector. The controller can be further configured to output the moments of the matrix to a computing device to estimate a trace of the matrix using the moments.
-
公开(公告)号：US20230195457A1
公开(公告)日：2023-06-22
申请号：US17556252
申请日：2021-12-20
CPC分类号： G06F9/30036 , G06F9/3001 , G06F17/16
摘要： Techniques are provided to implement hardware accelerated application of preconditioners to solve linear equations. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode entries of a preconditioning matrix which is storable in the array of cells. When the preconditioning matrix is stored in the array of cells, the processor is configured to apply the preconditioning matrix to a plurality of residual vectors by executing a process which includes performing analog matrix-vector multiplication operations on the preconditioning matrix and respective ones of the plurality of residual vectors to generate a plurality of output vectors used in one or more subsequent operations.
-
公开(公告)号：US20220300575A1
公开(公告)日：2022-09-22
申请号：US17207912
申请日：2021-03-22
发明人： Vasileios Kalantzis , Shashanka Ubaru , Haim Avron , Lior Horesh
IPC分类号： G06F17/16 , G06F16/901 , G06F16/22 , G06F16/23
摘要： Techniques for determining a count of triangles (tr) in a graph data structure using a crosspoint array is described. An adjacency matrix (a) representing the graph is mapped to the crosspoint array by configuring resistance values of crosspoint devices in the array. The count of triangles is initialized to zero (tr=0), and iteratively updated. The updating includes generating a first vector (x1) stochastically to include digital values in a predetermined range, which are converted into the voltage values. A multiplication of the adjacency matrix and the first vector (ax1) is computed using the crosspoint array. A second voltage vector (z1=ax1) is generated that includes voltage values representing the multiplication result. The adjacency matrix and the second voltage vector (z2=az1) are multiplied using the crosspoint array. The computer updates the number of triangles in the graph data structure as tr=tr+Z1T.
-
公开(公告)号：US20220207376A1
公开(公告)日：2022-06-30
申请号：US17134814
申请日：2020-12-28
发明人： Tayfun Gokmen , Oguzhan Murat Onen , Chai Wah Wu , Mark S. Squillante , Malte Johannes Rasch , Tomasz J. Nowicki , Wilfried Haensch , Lior Horesh , Vasileios Kalantzis , Vanessa Lopez-Marrero
摘要： Matrix inversion systems and methods are implemented using an analog resistive processing unit (RPU) array for hardware accelerated computing. A request is received from an application to compute an inverse matrix of a given matrix, and a matrix inversion process is performed in response to the received request. The matrix inversion process includes storing a first estimated inverse matrix of the given matrix in an array RPU cells, performing a first iterative process on the first estimated inverse matrix stored in the array of RPU cells to converge the first estimated inverse matrix to a second estimated inverse matrix of the given matrix, and reading the second estimated inverse matrix from the array of RPU cells upon completion of the first iterative process. An inverse matrix is returned to the application, wherein the returned inverse matrix is based, at least in part, on the second estimated inverse matrix.
-
公开(公告)号：US20210357540A1
公开(公告)日：2021-11-18
申请号：US16874819
申请日：2020-05-15
发明人： Lior Horesh , Oguzhan Murat Onen , Haim Avron , Tayfun Gokmen , Vasileios Kalantzis , Shashanka Ubaru
IPC分类号： G06F30/10
摘要： A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.
-
公开(公告)号：US20240296324A1
公开(公告)日：2024-09-05
申请号：US18356958
申请日：2023-07-21
IPC分类号： G06N3/08
CPC分类号： G06N3/08
摘要： A directed graph autoencoder device includes one or more memories and a processor coupled to the one or more memories and configured to implement a graph convolutional layer. The graph convolutional layer comprises a plurality of nodes and is configured to generate transformed dual vector representations by applying a source weight matrix and a target weight matrix to input dual vector representations of the plurality of nodes. The input dual vector representations comprise, for each node of the plurality of nodes, a source vector representation that corresponds to the node in its role as a source and a target vector representation that corresponds to the node in its role as a target. The graph convolutional layer is further configured to scale the transformed dual vector representations to generate scaled transformed dual vector representations. The graph convolutional layer is further configured to perform message passing using the scaled transformed dual vector representations.
-
公开(公告)号：US11907715B2
公开(公告)日：2024-02-20
申请号：US17556252
申请日：2021-12-20
CPC分类号： G06F9/30036 , G06F9/3001 , G06F17/16
摘要： Techniques are provided to implement hardware accelerated application of preconditioners to solve linear equations. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode entries of a preconditioning matrix which is storable in the array of cells. When the preconditioning matrix is stored in the array of cells, the processor is configured to apply the preconditioning matrix to a plurality of residual vectors by executing a process which includes performing analog matrix-vector multiplication operations on the preconditioning matrix and respective ones of the plurality of residual vectors to generate a plurality of output vectors used in one or more subsequent operations.
-
-
-
-
-
-
-
-
-
搜索结果
33 条记录 (耗时 0.021 秒)
