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公开(公告)号：US11790033B2
公开(公告)日：2023-10-17
申请号：US17023318
申请日：2020-09-16
CPC分类号： G06F17/12 , G06F9/4881 , G06F17/16 , G06N3/04 , G06N3/08
摘要： A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.
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公开(公告)号：US11520855B2
公开(公告)日：2022-12-06
申请号：US16874819
申请日：2020-05-15
发明人： Lior Horesh , Oguzhan Murat Onen , Haim Avron , Tayfun Gokmen , Vasileios Kalantzis , Shashanka Ubaru
摘要： A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.
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公开(公告)号：US11544061B2
公开(公告)日：2023-01-03
申请号：US17131034
申请日：2020-12-22
发明人： Malte Johannes Rasch , Oguzhan Murat Onen , Tayfun Gokmen , Chai Wah Wu , Mark S. Squillante , Tomasz J. Nowicki , Wilfried Haensch , Lior Horesh , Vasileios Kalantzis , Haim Avron
摘要： Methods and systems for solving a linear system include setting resistances in an array of settable electrical resistances in accordance with values of an input matrix. A series of input vectors is applied to the array as voltages to generate a series of respective output vectors. Each input vector in the series of vectors is updated based on comparison of the respective output vectors to a target vector. A solution of a linear system is determined that includes the input matrix based on the updated input vectors.
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公开(公告)号：US20180293209A1
公开(公告)日：2018-10-11
申请号：US15838992
申请日：2017-12-12
发明人： Tayfun Gokmen , Oguzhan Murat Onen
CPC分类号： G06F17/16 , G06F7/523 , G06F7/535 , G06F7/5443 , G06F2207/4814 , G06F2207/4824 , G06F2207/4828 , G06G7/16 , G06N3/0635 , G06N3/08
摘要： A method, computer program product, and circuit are provided for noise and bound management for a Resistive Processing Unit (RPU) array having an op-amp. The method includes reducing the noise in an output signal from the RPU array by using a largest value, in a sigma vector having a plurality of values, as a representation for a window for an input signal to the RPU array. The input signal to the RPU array is formed from the plurality of values. The method further includes sensing saturation at an output of the op-amp. The method also includes managing the bound to eliminate the saturation by reducing the plurality of values from which the input signal to the RPU is formed.
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公开(公告)号：US20220207376A1
公开(公告)日：2022-06-30
申请号：US17134814
申请日：2020-12-28
发明人： Tayfun Gokmen , Oguzhan Murat Onen , Chai Wah Wu , Mark S. Squillante , Malte Johannes Rasch , Tomasz J. Nowicki , Wilfried Haensch , Lior Horesh , Vasileios Kalantzis , Vanessa Lopez-Marrero
摘要： Matrix inversion systems and methods are implemented using an analog resistive processing unit (RPU) array for hardware accelerated computing. A request is received from an application to compute an inverse matrix of a given matrix, and a matrix inversion process is performed in response to the received request. The matrix inversion process includes storing a first estimated inverse matrix of the given matrix in an array RPU cells, performing a first iterative process on the first estimated inverse matrix stored in the array of RPU cells to converge the first estimated inverse matrix to a second estimated inverse matrix of the given matrix, and reading the second estimated inverse matrix from the array of RPU cells upon completion of the first iterative process. An inverse matrix is returned to the application, wherein the returned inverse matrix is based, at least in part, on the second estimated inverse matrix.
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公开(公告)号：US20210357540A1
公开(公告)日：2021-11-18
申请号：US16874819
申请日：2020-05-15
发明人： Lior Horesh , Oguzhan Murat Onen , Haim Avron , Tayfun Gokmen , Vasileios Kalantzis , Shashanka Ubaru
IPC分类号： G06F30/10
摘要： A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.
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公开(公告)号：US10325007B2
公开(公告)日：2019-06-18
申请号：US15479561
申请日：2017-04-05
发明人： Tayfun Gokmen , Oguzhan Murat Onen
摘要： A method, computer program product, and circuit are provided for noise and bound management for a Resistive Processing Unit (RN) array having an op-amp. The method includes reducing the noise in an output signal from the RPU array by using a largest value, in a sigma vector having a plurality of values, as a representation for a window for an input signal to the RPU array. The input signal to the RPU array is formed from the plurality of values. The method further includes sensing saturation at an output of the op-amp. The method also includes managing the bound to eliminate the saturation by reducing the plurality of values from which the input sign to the RPU is formed.
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公开(公告)号：US20180293208A1
公开(公告)日：2018-10-11
申请号：US15479561
申请日：2017-04-05
发明人： Tayfun Gokmen , Oguzhan Murat Onen
CPC分类号： G06F17/16 , G06F7/523 , G06F7/535 , G06F7/5443 , G06F2207/4814 , G06F2207/4824 , G06F2207/4828 , G06G7/16 , G06N3/0635 , G06N3/08
摘要： A method, computer program product, and circuit are provided for noise and bound management for a Resistive Processing Unit (RN) array having an op-amp. The method includes reducing the noise in an output signal from the RPU array by using a largest value, in a sigma vector having a plurality of values, as a representation for a window for an input signal to the RPU array. The input signal to the RPU array is formed from the plurality of values. The method further includes sensing saturation at an output of the op-amp. The method also includes managing the bound to eliminate the saturation by reducing the plurality of values from which the input sign to the RPU is formed.
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9.发明授权公开(公告)号：US11568217B2
公开(公告)日：2023-01-31
申请号：US16929172
申请日：2020-07-15
摘要： Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.
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公开(公告)号：US20220366005A1
公开(公告)日：2022-11-17
申请号：US17245801
申请日：2021-04-30
发明人： Tomasz J. Nowicki , Oguzhan Murat Onen , Tayfun Gokmen , Vasileios Kalantzis , Chai Wah Wu , Mark S. Squillante , Malte Johannes Rasch , Wilfried Haensch , Lior Horesh
摘要： Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.
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