公开(公告)号：US20020014900A1

公开(公告)日：2002-02-07

申请号：US09915119

申请日：2001-07-25

Applicant: Intersil Americas Inc.

Inventor： James W. Swonger ,  Brent R. Doyle

IPC: H03B001/00 ,  H03K003/00

CPC classification number: H03K17/063 ,  H03K2217/0036

Abstract: The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

Abstract translation: 电路和方法将逻辑电平输入信号转换为高电压电平的信号，以驱动诸如功率MOSFET的功率器件，同时最小化功耗。 用于驱动功率器件的电路包括低侧栅极驱动器和与其相邻的高边栅极驱动器。 高侧栅极驱动器包括高端栅极驱动器逻辑输入，高边栅极驱动器输出，连接在高侧栅极驱动器逻辑输入和高侧栅极驱动器输出之间的锁存器以及接收锁存器的输出的控制电路 以及基于所述锁存器的输出来控制从所述高侧栅极驱动器逻辑输入到所述锁存器的信号。

公开(公告)号：US20020060585A1

公开(公告)日：2002-05-23

申请号：US09973106

申请日：2001-10-09

Applicant: INTERSIL AMERICAS INC.

Inventor： Brent R. Doyle ,  James W. Swonger

IPC: H03K005/22

CPC classification number: H03K5/24

Abstract: An analog comparator architecture has improved immunity to single event effects and variations in input offset voltage. A conventional single analog comparator-based circuit is replaced with plural comparators, driving a nullmajority votenull logic block. The effective input offset voltage of the multi-comparator design is the middle one of the individual comparators' input offset voltages. A single event upset on any comparator may momentarily perturb its output into the incorrect state; however, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset. In addition, where a heavy ion strike on any comparator's bias current source causes a momentary loss of bias current, this upsets only one comparator, so that the output of the voting logic block is unaffected.

Abstract translation: 模拟比较器架构提高了对单个事件效应的抵抗力和输入失调电压的变化。 传统的基于单个模拟比较器的电路被多个比较器替代，驱动“多数投票”逻辑块。 多比较器设计的有效输入失调电压是各个比较器输入失调电压的中间值。 任何比较器上的单个事件不适应可能会暂时将其输出扰乱到不正确的状态; 然而，多数表决逻辑块的输出将保持在正确的状态，因为只有一个比较器不舒服。 此外，当任何比较器的偏置电流源发生重离子撞击时，均会导致偏置电流的瞬时损耗，因此这只会扰乱一个比较器，因此投票逻辑块的输出不受影响。

公开(公告)号：US20020020858A1

公开(公告)日：2002-02-21

申请号：US09918208

申请日：2001-07-30

Applicant: Intersil Americas Inc,

Inventor： Brent R. Doyle

IPC: H01L027/10 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L27/0921

Abstract: A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at nullV (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.

Abstract translation: 接合隔离的互补金属氧化物半导体（CMOS）晶体管器件包括第一导电类型的衬底和形成在衬底内并具有与第一导电类型相反的第二导电类型的第一和第二掩埋层。 各自的第一和第二导电性的第一和第二阱区形成在相应的第一和第二埋层之上。 在相应的第一和第二阱区域中形成NMOS晶体管和PMOS晶体管。 NMOS晶体管的掩埋层处于-V（通常接地），并且PMOS晶体管的掩埋层被偏置在正电源电压并且与NMOS晶体管充分隔开以改善单个事件效应的出现。