公开(公告)号：US20170297911A1

公开(公告)日：2017-10-19

申请号：US15298499

申请日：2016-10-20

Applicant: InvenSense, Inc.

Inventor： Jong II SHIN ,  Peter SMEYS ,  Bongsang KIM

IPC: B81C1/00 ,  B81B3/00 ,  B81B7/02

CPC classification number: B81C1/00682 ,  B81B3/0078 ,  B81B7/02 ,  B81C1/00333 ,  B81C2203/0118 ,  B81C2203/036

Abstract: Provided herein is a method including forming a cavity in a first side of a first silicon wafer. An oxide layer is formed on the first side and in the cavity. The first side of the first silicon wafer is bonded to a first side of a second silicon wafer, and a gap control structure is deposited on a second side of the second silicon wafer. A MEMS structure is formed in the second silicon wafer. The second side of the second silicon wafer is eutecticly bonded to the third silicon wafer, and the eutectic bonding includes pressing the second silicon wafer to the third silicon wafer.