公开(公告)号：US20170073217A1

公开(公告)日：2017-03-16

申请号：US15366495

申请日：2016-12-01

Applicant: INVENSENSE, INC.

Inventor： Peter SMEYS ,  Jong Il SHIN ,  Jongwoo SHIN

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

Abstract translation: 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS器件还包括第二衬底。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

公开(公告)号：US20190241432A1

公开(公告)日：2019-08-08

申请号：US16389472

申请日：2019-04-19

Applicant: InvenSense, Inc.

Inventor： Jong Il SHIN ,  Peter SMEYS ,  Bongsang KIM

IPC: B81C1/00 ,  B81B3/00

Abstract: Provided herein is an apparatus including a cavity in a first side of a first silicon wafer, and an oxide layer on the first side and in the cavity. A first side of a second silicon wafer is bonded to the first side of the first silicon wafer. A gap control structure is on a second side of the second silicon wafer, and a MEMS structure in the second silicon wafer. A eutectic bond is bonding the second side of the second silicon wafer to a third silicon wafer. A lower cavity is between the second side of the silicon wafer and the third silicon wafer, wherein the gap control structure is outside of the lower cavity and the eutectic bond.

公开(公告)号：US20170297911A1

公开(公告)日：2017-10-19

申请号：US15298499

申请日：2016-10-20

Applicant: InvenSense, Inc.

Inventor： Jong II SHIN ,  Peter SMEYS ,  Bongsang KIM

IPC: B81C1/00 ,  B81B3/00 ,  B81B7/02

CPC classification number: B81C1/00682 ,  B81B3/0078 ,  B81B7/02 ,  B81C1/00333 ,  B81C2203/0118 ,  B81C2203/036

Abstract: Provided herein is a method including forming a cavity in a first side of a first silicon wafer. An oxide layer is formed on the first side and in the cavity. The first side of the first silicon wafer is bonded to a first side of a second silicon wafer, and a gap control structure is deposited on a second side of the second silicon wafer. A MEMS structure is formed in the second silicon wafer. The second side of the second silicon wafer is eutecticly bonded to the third silicon wafer, and the eutectic bonding includes pressing the second silicon wafer to the third silicon wafer.

公开(公告)号：US20160060100A1

公开(公告)日：2016-03-03

申请号：US14559715

申请日：2014-12-03

Applicant: InvenSense, Inc.

Inventor： Peter SMEYS ,  Mozafar MAGHSOUDNIA

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B7/008 ,  B81C1/00238 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2924/00014

Abstract: A method and system for providing a MEMS sensor integrated with a flip chip are disclosed. In a first aspect, the system comprises a MEMS sensor, at least one flip chip coupled to the MEMS sensor, and at least one through-silicon via (TSV) that electrically connects the at least one flip chip to the MEMS sensor. In a second aspect, the system comprises a MEMS sensor that includes a CMOS coupled to a MEMS structure, wherein the CMOS comprises a substrate coupled to an interconnect in contact with the MEMS structure. The system further comprises a plurality of flip chips coupled to the substrate, a plurality of TSV that electrically connect the plurality of flip chips to the interconnect, and a plurality of layers on the substrate to provide electrical connections between the plurality of flip chips and from the plurality of flip chips to at least one external component.

Abstract translation: 公开了一种用于提供与倒装芯片集成的MEMS传感器的方法和系统。 在第一方面，该系统包括MEMS传感器，耦合到MEMS传感器的至少一个倒装芯片以及将至少一个倒装芯片电连接到MEMS传感器的至少一个穿硅通孔（TSV）。 在第二方面，该系统包括MEMS传感器，其包括耦合到MEMS结构的CMOS，其中CMOS包括耦合到与MEMS结构接触的互连的衬底。 该系统还包括耦合到衬底的多个倒装芯片，将多个倒装芯片电连接到互连件的多个TSV以及衬底上的多个层，以提供多个倒装芯片之间的电连接 所述多个倒装芯片至少一个外部部件。

公开(公告)号：US20160002028A1

公开(公告)日：2016-01-07

申请号：US14752718

申请日：2015-06-26

Applicant: InvenSense, Inc.

Inventor： Peter SMEYS

IPC: B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/02 ,  B81C1/00246 ,  B81C2201/0197 ,  B81C2203/0792

Abstract: A method of providing a CMOS-MEMS structure is disclosed. The method comprises patterning a first top metal on a MEMS actuator substrate and a second top metal on a CMOS substrate. Each of the MEMS actuator substrate and the CMOS substrate include an oxide layer thereon. The method includes etching each of the oxide layers on the MEMS actuator substrate and the base substrate, utilizing a first bonding step to bond the first patterned top metal of the MEMS actuator substrate to the second patterned top metal of the base substrate. Finally the method includes etching an actuator layer into the MEMS actuator substrate and utilizing a second bonding step to bond the MEMS actuator substrate to a MEMS handle substrate.

Abstract translation: 公开了一种提供CMOS-MEMS结构的方法。 该方法包括将MEMS致动器基板上的第一顶部金属和CMOS基板上的第二顶部金属图案化。 MEMS致动器基板和CMOS基板中的每一个在其上包括氧化物层。 该方法包括利用第一结合步骤将MEMS致动器基板的第一图案化顶部金属与基底基板的第二图案化顶部金属结合来蚀刻MEMS致动器基板和基底基板上的每个氧化物层。 最后，该方法包括将致动器层蚀刻到MEMS致动器基板中，并利用第二结合步骤将MEMS致动器基板结合到MEMS手柄基板。

公开(公告)号：US20160362296A1

公开(公告)日：2016-12-15

申请号：US14738645

申请日：2015-06-12

Applicant: InvenSense, Inc.

Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS

IPC: B81C1/00

CPC classification number: B81C1/00301 ,  B81C2201/013 ,  B81C2203/036 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5226

Abstract: A method for forming a MEMS device is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate, where includes a handle layer, a device layer and an insulating layer in between. The method includes the sequential steps of: providing a standoff on the device layer; etching a via through the device layer and the insulating layer; providing a contact layer within the via, wherein the contact layer provides electrical connection between the device layer and the handle layer; providing a bonding layer on the standoff; and bonding the bonding layer to pads on the base substrate.

Abstract translation: 公开了一种用于形成MEMS器件的方法。 MEMS器件包括MEMS衬底和基底衬底。 MEMS衬底，其中包括手柄层，器件层和绝缘层。 该方法包括以下顺序步骤：在设备层上提供间隔; 通过器件层和绝缘层蚀刻通孔; 在所述通孔内提供接触层，其中所述接触层在所述器件层和所述手柄层之间提供电连接; 在支架上提供粘合层; 以及将所述结合层粘合到所述基底基板上的焊盘。

公开(公告)号：US20160221819A1

公开(公告)日：2016-08-04

申请号：US14748012

申请日：2015-06-23

Applicant: InvenSense, Inc.

Inventor： Peter SMEYS ,  Jong Il SHIN ,  Jongwoo SHIN

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

Abstract translation: 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS装置还包括第二基板。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

公开(公告)号：US20160075554A1

公开(公告)日：2016-03-17

申请号：US14850860

申请日：2015-09-10

Applicant: InvenSense, Inc.

Inventor： Anatole HUANG ,  Jongwoo SHIN ,  Peter SMEYS ,  Cerina ZHANG ,  Jong Il SHIN

IPC: B81B7/00 ,  B81C1/00

Abstract: A MEMS device having a channel configured to avoid particle contamination is disclosed. The MEMS device includes a MEMS substrate and a base substrate. The MEMS substrate includes a MEMS device area, a seal ring and a channel. The seal ring provides for dividing the MEMS device area into a plurality of cavities, wherein at least one of the plurality of cavities includes one or more vent holes. The channel is configured between the one or more vent holes and the MEMS device area. Preferably, the channel is configured to minimize particles entering the MEMS device area directly. The base substrate is coupled to the MEMS device substrate.

Abstract translation: 公开了具有被配置为避免颗粒污染的通道的MEMS器件。 MEMS器件包括MEMS衬底和基底衬底。 MEMS衬底包括MEMS器件区域，密封环和沟道。 密封环提供将MEMS器件区域分成多个空腔，其中多个空腔中的至少一个包括一个或多个通气孔。 通道配置在一个或多个通气孔和MEMS器件区域之间。 优选地，通道被配置为使直接进入MEMS器件区域的颗粒最小化。 基底衬底耦合到MEMS器件衬底。

公开(公告)号：US20150311178A1

公开(公告)日：2015-10-29

申请号：US14696994

申请日：2015-04-27

Applicant: InvenSense, Inc.

Inventor： Jong Il SHIN ,  Peter SMEYS ,  Jongwoo SHIN

IPC: H01L23/00

CPC classification number: H01L24/83 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792 ,  H01L2224/83065 ,  H01L2224/83805 ,  H01L2224/83951

Abstract: Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.

Abstract translation: 公开了粘合两个晶片的方法。 在一个方面，第一晶片包括集成电路，第二晶片包括MEMS器件。 该方法包括在第一晶片上的金属上沉积接合焊盘，并且利用第一和第二温度将第一晶片顺序地结合到第二晶片。 第二晶片在第一温度下接合到接合焊盘，并且接合焊盘和金属在第二温度下结合。 在另一方面，包括集成电路的第一晶片，所述第二晶片包括MEMS器件。 该方法包括在第一晶片和第二晶片之一上的金属上沉积接合焊盘，并且通过直接键合界面在第一温度下将第一晶片接合到第二晶片。 该方法包括在第二温度下将接合焊盘接合到金属。

公开(公告)号：US20180009654A1

公开(公告)日：2018-01-11

申请号：US15711890

申请日：2017-09-21

Applicant: InvenSense, Inc.

Inventor： Peter SMEYS ,  Martin LIM

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B2201/0207 ,  B81B2201/0214 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2203/0315 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A sensor chip includes a first substrate with a first surface and a second surface including at least one CMOS circuit, a first MEMS substrate with a first surface and a second surface on opposing sides of the first MEMS substrate, a second substrate, a second MEMS substrate, and a third substrate including at least one CMOS circuit. The first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the first MEMS substrate. The second surface of the first MEMS substrate is attached to the second substrate. The first substrate, the first MEMS substrate, the second substrate and the packaging substrate are provided with electrical inter-connects.