BUFFERED FINFET DEVICE
    1.
    发明申请
    BUFFERED FINFET DEVICE 有权
    缓冲FINFET器件

    公开(公告)号:US20130043536A1

    公开(公告)日:2013-02-21

    申请号:US13214102

    申请日:2011-08-19

    IPC分类号: H01L27/12 H01L21/336

    摘要: One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

    摘要翻译: 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层,缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性,并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例,方面和特征。