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    Method and apparatus for adaptive bus coding for low power deep sub-micron designs
    1.
    发明授权
    Method and apparatus for adaptive bus coding for low power deep sub-micron designs 失效
    用于低功率深亚微米设计的自适应总线编码的方法和装置

    公开(公告)号：US06741190B2

    公开(公告)日：2004-05-25

    申请号：US10422728

    申请日：2003-04-25

    申请人： Jörg Henkel ,  Haris Lekatsas

    发明人： Jörg Henkel ,  Haris Lekatsas

    IPC分类号： H03M700

    CPC分类号： H04L25/49 ,  H04L5/20

    摘要： The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.

    摘要翻译： 互连的功耗开始对系统的总功耗产生重大影响。 除了增加总线（长度，宽度）等，这主要是由于深度亚微米效应，其中总线线路（线对线）之间的耦合电容与基极电容（线对金属）相同数量级 -层）。 在这一点上，为了减少功率而仅仅解决转换的最小化的编码方案不再有效地起作用。 提出了一种准确地模拟耦合电容的物理总线模型，提出了具有部分自适应编码方案的信号总线编码/解码装置，并考虑了耦合效应。 编码方案不承担特定应用的任何先验知识。

    Method and apparatus for object code compression and decompression for computer systems
    2.
    发明授权
    Method and apparatus for object code compression and decompression for computer systems 有权
    用于计算机系统的目标代码压缩和解压缩的方法和装置

    公开(公告)号：US06732256B2

    公开(公告)日：2004-05-04

    申请号：US10462675

    申请日：2003-06-17

    申请人： Jörg Henkel ,  Wayne Wolf ,  Haris Lekatsas

    发明人： Jörg Henkel ,  Wayne Wolf ,  Haris Lekatsas

    IPC分类号： G06F930

    CPC分类号： G06F9/30178 ,  G06F9/30156 ,  G06F9/30185

    摘要： A code compression method and apparatus for system-level power optimization that lessens the requirements imposed on main memory size. The apparatus utilizes a post-cache architecture that has a decompression engine that decompresses compressed object code instructions using dictionary look-up tables, branching instruction controllers and mathematical derivations based on bit toggling. The decompression engine extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.

    摘要翻译： 用于系统级功率优化的代码压缩方法和装置，其减轻对主存储器大小的要求。 该装置使用具有解压缩引擎的缓存后架构，其使用字典查找表，分支指令控制器和基于位切换的数学推导解压缩压缩目标代码指令。 解压缩引擎使用总线压缩技术从存储器或指令/数据高速缓存中提取压缩指令，以在压缩指令/数据穿过总线时节省功率。

    Object code compression using different schemes for different instruction types
    3.
    发明授权
    Object code compression using different schemes for different instruction types 有权
    使用不同方案的对象代码压缩用于不同的指令类型

    公开(公告)号：US06691305B1

    公开(公告)日：2004-02-10

    申请号：US09556927

    申请日：2000-04-21

    申请人： Jörg Henkel ,  Wayne Wolf ,  Haris Lekatsas

    发明人： Jörg Henkel ,  Wayne Wolf ,  Haris Lekatsas

    IPC分类号： G06F945

    CPC分类号： G06F9/30178 ,  G06F9/30156 ,  G06F9/30185

    摘要： A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions. The invention also has an apparatus utilizing a post-cache architecture that has a decompression engine that decompresses instructions that have been compressed using the method of the invention. The apparatus extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.

    摘要翻译： 用于系统级功率优化的代码压缩方法，可减轻对主内存大小的要求。 该方法降低了包括CPU，指令高速缓存，数据高速缓存，主存储器，数据总线和地址总线的完整系统的功耗。 该方法包括从可执行代码提取可压缩指令和数据部分，创建提取的代码部分的数学模型，根据它们的操作代码对压缩指令进行分类，提取部分中的各个指令。 当通过使用总线压缩从存储器中提取时，压缩指令进一步被压缩。 该方法还体现在具有处理器和存储器的计算机系统中，适于执行压缩提取的指令部分的方法的步骤。 此外，该方法体现在一种计算机程序产品上，该计算机程序产品具有适于执行压缩所提取的指令部分的方法的步骤的软件指令。 本发明还具有使用具有解压缩引擎的缓存后结构的装置，该解压缩引擎使用本发明的方法对已经被压缩的指令进行解压缩。 该装置使用总线压缩技术从存储器或指令/数据高速缓存中提取压缩指令，以在压缩指令/数据穿过总线时节省功率。

    Method and apparatus for adaptive bus coding for low power deep sub-micron designs
    4.
    发明授权
    Method and apparatus for adaptive bus coding for low power deep sub-micron designs 失效
    用于低功率深亚微米设计的自适应总线编码的方法和装置

    公开(公告)号：US06583735B2

    公开(公告)日：2003-06-24

    申请号：US09920854

    申请日：2001-08-03

    申请人： Jörg Henkel ,  Haris Lekatsas

    发明人： Jörg Henkel ,  Haris Lekatsas

    IPC分类号： H03M734

    CPC分类号： H04L25/49 ,  H04L5/20

    摘要： The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.

    摘要翻译： 互连的功耗开始对系统的总功耗产生重大影响。 除了增加总线（长度，宽度）等，这主要是由于深度亚微米效应，其中总线线路（线对线）之间的耦合电容与基极电容（线对金属）相同数量级 -层）。 在这一点上，为了减少功率而仅仅解决转换的最小化的编码方案不再有效地起作用。 提出了一种准确地模拟耦合电容的物理总线模型，提出了具有部分自适应编码方案的信号总线编码/解码装置，并考虑了耦合效应。 编码方案不承担特定应用的任何先验知识。

    Hardware/software platform for rapid prototyping of code compression technologies
    5.
    发明授权
    Hardware/software platform for rapid prototyping of code compression technologies 有权
    用于快速原型代码压缩技术的硬件/软件平台

    公开(公告)号：US07203935B2

    公开(公告)日：2007-04-10

    申请号：US10309824

    申请日：2002-12-05

    申请人： Srimat Chakradhar ,  Jörg Henkel ,  Venkata Jakkula ,  Haris Lekatsas ,  Murugan Sankaradass

    发明人： Srimat Chakradhar ,  Jörg Henkel ,  Venkata Jakkula ,  Haris Lekatsas ,  Murugan Sankaradass

    IPC分类号： G06F9/45 ,  G06F9/30

    CPC分类号： G06F9/32 ,  G06F9/30178 ,  G06F9/445

    摘要： A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.

    摘要翻译： 一种用于程序的代码压缩的方法，所述方法包括从数据中分离代码。 在压缩和未压缩空间之间进行地址映射所需的软件转换被引入到代码中。 获得关于发生指令频率的统计，其中所述统计包括两个连续指令的出现频率。 该程序被解析以识别指令或指令对的发生。 所识别的指令被替换为压缩总线字表的地址。 从未压缩地址到压缩地址生成地址映射。