公开(公告)号：US20170373012A1

公开(公告)日：2017-12-28

申请号：US15585659

申请日：2017-05-03

Applicant: J-Devices Corporation

Inventor： Toshiyuki INAOKA ,  Yuichiro YOSHIKAWA ,  Atsuhiro URATSUJI ,  Katsushi YOSHIMITSU

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747

Abstract: An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.

公开(公告)号：US20170256453A1

公开(公告)日：2017-09-07

申请号：US15409631

申请日：2017-01-19

Applicant: J-DEVICES CORPORATION

Inventor： Takahiro YADA ,  Katsushi YOSHIMITSU

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/56 ,  H01L21/304 ,  H01L25/065 ,  H01L23/31

Abstract: A manufacturing method of a semiconductor package which improves productivity and can manufacture high-quality semiconductor packages is provided. The manufacturing method of a semiconductor package includes arranging a plurality of semiconductor devices at intervals on a first surface side of a support substrate, forming a first insulating resin layer forming wiring connected to each of the plurality of semiconductor devices and embeds the plurality of semiconductor devices, cutting from the first surface side in areas between the plurality of semiconductor devices, forming a first groove portion penetrating the first insulating resin layer and exposing the support substrate, and dividing individual semiconductor packages by forming a resist pattern having openings arranged corresponding to the first groove portion on a second surface on the opposite side of the first surface, etching the openings from the second surface side, and forming a second groove portion on the second surface side

公开(公告)号：US20180174975A1

公开(公告)日：2018-06-21

申请号：US15884979

申请日：2018-01-31

Applicant: J-Devices Corporation

Inventor： Toshiyuki INAOKA ,  Yuichiro YOSHIKAWA ,  Atsuhiro URATSUJI ,  Katsushi YOSHIMITSU

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L21/56

CPC classification number: H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747

Abstract: An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.