公开(公告)号：US12119281B2

公开(公告)日：2024-10-15

申请号：US17394093

申请日：2021-08-04

Applicant: Qorvo US, Inc.

Inventor： Dylan Murdock

IPC: H01L23/31 ,  H01L23/04 ,  H01L23/10 ,  H01L23/29 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/3142 ,  H01L23/04 ,  H01L23/10 ,  H01L23/291 ,  H01L23/315 ,  H01L23/3736 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48225 ,  H01L2224/49176 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01403 ,  H01L2924/05432 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/173 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/3512

Abstract: The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

公开(公告)号：US20240339390A1

公开(公告)日：2024-10-10

申请号：US18666369

申请日：2024-05-16

Applicant: Lodestar Licensing Group LLC

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US12068324B2

公开(公告)日：2024-08-20

申请号：US17358790

申请日：2021-06-25

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L27/10 ,  H01G4/228 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L49/02 ,  H01L23/50 ,  H01L25/10

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

公开(公告)号：US20240178256A1

公开(公告)日：2024-05-30

申请号：US18431716

申请日：2024-02-02

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Rajesh Katkar

IPC: H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/18 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2924/15153 ,  H01L2924/16235

Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

公开(公告)号：US20240176066A1

公开(公告)日：2024-05-30

申请号：US18434443

申请日：2024-02-06

Applicant: Lightmatter, Inc.

Inventor： Sukeshwar Kannan ,  Carl Ramey ,  Jon Elmhurst ,  Darius Bunandar ,  Nicholas C. Harris

IPC: G02B6/12 ,  G02B6/42 ,  H01L23/13 ,  H01L23/50 ,  H01L23/538 ,  H01L25/16 ,  H05K1/18

CPC classification number: G02B6/12 ,  H01L23/50 ,  H05K1/183 ,  G02B6/4274 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/167 ,  H01L2924/15153

Abstract: Described herein are photonic communication platforms and related packages. In one example, a photonic package includes a substrate carrier having a recess formed through the top surface of the substrate carrier. The substrate carrier may be made of a ceramic laminate. A photonic substrate including a plurality of photonic modules is disposed in the recess. The photonic modules may be patterned using a common photomask, and as a result, may share a same layer pattern. A plurality of electronic dies may be positioned on top of respective photonic modules. The photonic modules enable communication among the dies in the optical domain. Power delivery substrates may be used to convey electric power from the substrate carrier to the electronic dies and to the photonic substrate. Power delivery substrates may be implemented, for example, using bridge dies or interposers (e.g., silicon or organic interposers).

公开(公告)号：US20240121895A1

公开(公告)日：2024-04-11

申请号：US18388737

申请日：2023-11-10

Applicant: Nitride Global Inc.

Inventor： Jason Schmitt

IPC: H05K1/05 ,  B32B15/16 ,  H01L23/14

CPC classification number: H05K1/053 ,  B32B15/16 ,  H01L23/142 ,  H01L2924/13055 ,  H01L2924/15153

Abstract: The disclosure provides an insulated metal substrate (IMS) including a substrate having a first side and a second side. The IMS may also include a first dielectric layer on the first side of the substrate. The dielectric layer may include a metal-based oxynitride and/or a metalloid-based oxynitride layer, oxygen is from 0.1 at % to 49.9 at %, nitrogen is from 0.1 at % to 49.9 at % and a sum of oxygen and nitrogen is about 50 at %. The first dielectric layer comprises a material selected from a group consisting of aluminum oxynitride (AlON), aluminum oxyhydronitride (AlHON), aluminum oxycarbonitride (AlCON), SiGeON, GaON, SiON, and GeON. The substrate comprises one of Cu, Al, AlSi, C—Al, W—Cu, or Ti.

公开(公告)号：US20240112966A1

公开(公告)日：2024-04-04

申请号：US18478837

申请日：2023-09-29

Applicant: Azimuth Industrial Company, Inc.

Inventor： David Lee

IPC: H01L23/13 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/08238 ,  H01L2224/09181 ,  H01L2224/09183 ,  H01L2224/16168 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/80895 ,  H01L2224/81191 ,  H01L2924/15153

Abstract: Implementations generally relate to a multisided integrated circuit assembly. In some implementations, an assembly includes an integrated circuit (IC) chip having IC contact terminals. The assembly further includes surface interfaces coupled to the IC chip, where at least one first surface interface and at least one second surface interface of the surface interfaces are configured to couple to a motherboard. The assembly further includes surface contact terminals on the surface interfaces, where the surface contact terminals couple to the IC contact terminals, and where at least one subset of the surface contact terminals also couples to at least one subset of motherboard contact terminals on the motherboard.

公开(公告)号：US20240079393A1

公开(公告)日：2024-03-07

申请号：US18218673

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Heejung HWANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15174

Abstract: A semiconductor package includes a package substrate including a substrate cavity, the substrate cavity extending from an upper surface of the package substrate toward a lower surface of the package substrate, a wiring interposer attached to the package substrate, a memory semiconductor structure attached to a lower surface of the wiring interposer, at least a portion of the memory semiconductor structure art being accommodated in the substrate cavity, a logic semiconductor chip attached to an upper surface of the wiring interposer, a conductive spacer spaced apart from the logic semiconductor chip in a horizontal direction, the conductive spacer being attached to the upper surface of the wiring interposer and overlapping the memory semiconductor structure in a vertical direction, and a heat dissipation member over the logic semiconductor chip and the conductive spacer.

公开(公告)号：US11862525B2

公开(公告)日：2024-01-02

申请号：US17695757

申请日：2022-03-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tsung-Yu Lin ,  Pei-Yu Wang ,  Chung-Wei Hsu

IPC: H01L23/10 ,  H01L23/00 ,  H01L23/053 ,  H01L21/50 ,  H01L33/48 ,  H01L23/04 ,  G01L19/14

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L23/04 ,  H01L23/053 ,  H01L24/48 ,  H01L33/486 ,  G01L19/14 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/1659 ,  H01L2924/16195 ,  H01L2924/17151 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

公开(公告)号：US11800639B2

公开(公告)日：2023-10-24

申请号：US18115218

申请日：2023-02-28

Applicant: LG INNOTEK CO., LTD.

Inventor： Jun Young Lim ,  Woong Sik Kim ,  Hyung Kyu Yoon ,  Min Hwan Kim

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/28 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H05K1/14 ,  H05K3/18

CPC classification number: H05K1/0281 ,  H01L21/481 ,  H01L21/4821 ,  H01L23/4985 ,  H01L24/16 ,  H05K1/0271 ,  H05K1/144 ,  H05K3/18 ,  H05K3/28 ,  H01L21/4867 ,  H01L23/49827 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15153 ,  H05K1/189 ,  H05K2201/055 ,  H05K2201/10128

Abstract: A flexible circuit board and an electronic device including a flexible circuit board are provided. The flexible circuit board may include a substrate having a bending area and a non-bending area, a wiring pattern layer provided on the bending area and the non-bending area, a plating layer provided on the wiring pattern layer and including an open area in an area corresponding to the bending area, and a protective layer that directly contacts one surface of the wiring pattern layer exposed at the open area and a side surface of the plating layer. The protective layer may have a larger thickness than a thickness of the plating layer.