公开(公告)号：US10224256B2

公开(公告)日：2019-03-05

申请号：US15625464

申请日：2017-06-16

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu Machida ,  Kazuhiko Kitano

IPC: H01L21/48 ,  H01L23/14 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/552 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

公开(公告)号：US09635762B2

公开(公告)日：2017-04-25

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Hiroshi Demachi ,  Takeshi Miyakoshi ,  Tomoshige Chikai ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Takashi Nakamura ,  Hirokazu Honda ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/02 ,  H01L23/10 ,  H05K1/18 ,  H01L23/367 ,  H05K1/02 ,  H01L25/10 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

公开(公告)号：US09595488B2

公开(公告)日：2017-03-14

申请号：US15010988

申请日：2016-01-29

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiro Tanaka

IPC: H01L23/52 ,  H01L29/40 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49513 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the semiconductor element is fixed using a first metal, and a first pattern formed by a second metal, the first pattern being arranged on one part of the surface, wherein the second metal has a greater wetting characteristic than the surface when the first metal is melted.

Abstract translation: 根据本发明的一个实施例的半导体器件包括半导体元件，具有使用第一金属固定半导体元件的表面的岛和由第二金属形成的第一图案，第一图案被布置在一个上 表面的一部分，其中当第一金属熔化时，第二金属具有比表面更大的润湿特性。

公开(公告)号：US09553052B2

公开(公告)日：2017-01-24

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Toshihiro Iwasaki ,  Tomoshige Chikai ,  Kiminori Ishido ,  Shinji Watanabe ,  Michiaki Tamakawa

IPC: H01L29/82 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与存储元件的侧面隔开一定距离地配置的软磁性材料，以便部分地或全部地包围存储元件侧表面，所述磁屏蔽部磁性地连接到软磁 层。

公开(公告)号：US20160181194A1

公开(公告)日：2016-06-23

申请号：US14964121

申请日：2015-12-09

Applicant: J-Devices Corporation

Inventor： Yoshihiko IKEMOTO ,  Shigenori SAWACHI ,  Fumihiko TANIGUCHI ,  Akio KATSUMATA

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/3142 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5227 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267

Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.

Abstract translation: 本发明提供一种半导体器件，其中金属平板中的涡电流的产生减小，并且即使使用金属平板作为支撑件，也提高了半导体器件的RF电路的Q值。

公开(公告)号：US20160079204A1

公开(公告)日：2016-03-17

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。

公开(公告)号：US20200035582A1

公开(公告)日：2020-01-30

申请号：US16592213

申请日：2019-10-03

Applicant: J-DEVICES CORPORATION

Inventor： Masao HIROBE

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/04 ,  H01L23/00

Abstract: There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate.

公开(公告)号：US10388625B2

公开(公告)日：2019-08-20

申请号：US15290557

申请日：2016-10-11

Applicant: J-DEVICES CORPORATION

Inventor： Minoru Kai

IPC: H01L21/68 ,  H01L21/67 ,  H01L23/00

Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.

公开(公告)号：US10157760B2

公开(公告)日：2018-12-18

申请号：US15600082

申请日：2017-05-19

Applicant: J-DEVICES CORPORATION

Inventor： Minoru Kai

IPC: H01L21/68 ,  H01L21/67 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor manufacturing apparatus comprises a stage connected to a vacuum generator to suction a semiconductor wafer including a plurality of semiconductor chips, a suction control unit connected to a connecting portion of the stage and the vacuum generator to control the connection of the stage and the vacuum generator, a pickup unit connected to a movement control unit simultaneously picking up the plurality of semiconductor chips, and a control unit controlling movement and rotation of the pickup unit and controlling the suction control unit, the control unit is connected to the movement control unit. The pickup unit converts an interval of the plurality of semiconductor chips to a predetermined pitch and holds the pitch. The pickup unit moves the plurality of semiconductor chips from the stage to mounting positions of a supporting substrate and simultaneously adheres the plurality of semiconductor chips at the mounting positions by the control unit.

公开(公告)号：US10096564B2

公开(公告)日：2018-10-09

申请号：US15481848

申请日：2017-04-07

Applicant: J-DEVICES CORPORATION

Inventor： Toshiyuki Inaoka ,  Atsuhiro Uratsuji

IPC: H01L21/44 ,  H01L23/00

Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.